diff --git a/.pick_status.json b/.pick_status.json
index 9d2efddb0d7..314761787b0 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -314,7 +314,7 @@
         "description": "anv: Fix PAT entry for userptr in integrated GPUs",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "060439bdf0e74f0f2e255d0a81b5356f9a2f5457",
         "notes": null
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 97861da01b9..612caa5c553 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -5116,13 +5116,15 @@ const struct intel_device_info_pat_entry *
 anv_device_get_pat_entry(struct anv_device *device,
                          enum anv_bo_alloc_flags alloc_flags)
 {
+   if (alloc_flags & ANV_BO_ALLOC_IMPORTED)
+      return &device->info->pat.cached_coherent;
+
    /* PAT indexes has no actual effect in DG2 and DG1, smem caches will always
     * be snopped by GPU and lmem will always be WC.
     * This might change in future discrete platforms.
     */
    if (anv_physical_device_has_vram(device->physical)) {
-      if ((alloc_flags & ANV_BO_ALLOC_NO_LOCAL_MEM) ||
-          (alloc_flags & ANV_BO_ALLOC_IMPORTED))
+      if (alloc_flags & ANV_BO_ALLOC_NO_LOCAL_MEM)
          return &device->info->pat.cached_coherent;
       return &device->info->pat.writecombining;
    }