radeonsi: add flag L2_STREAM for minimal cache usage
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8f6e06d160
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0c5429cc73
3 changed files with 13 additions and 6 deletions
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@ -294,11 +294,13 @@
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#define V_500_GDS 1 /* program SAS to 1 as well */
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#define V_500_DATA 2
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#define V_500_SRC_ADDR_TC_L2 3 /* new for CIK */
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#define S_500_DST_CACHE_POLICY(x) (((unsigned)(x) & 0x3) << 25) /* CIK+ */
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#define S_500_DST_SEL(x) (((unsigned)(x) & 0x3) << 20)
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#define V_500_DST_ADDR 0
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#define V_500_GDS 1 /* program DAS to 1 as well */
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#define V_500_NOWHERE 2 /* new for GFX9 */
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#define V_500_DST_ADDR_TC_L2 3 /* new for CIK */
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#define S_500_SRC_CACHE_POLICY(x) (((unsigned)(x) & 0x3) << 13) /* CIK+ */
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#define S_500_ENGINE(x) ((x) & 0x1)
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#define V_500_ME 0
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#define V_500_PFP 1
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@ -88,15 +88,19 @@ static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
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/* Src and dst flags. */
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if (sctx->chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) &&
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src_va == dst_va)
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src_va == dst_va) {
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header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
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else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS)
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header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
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} else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS) {
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header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2) |
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S_500_DST_CACHE_POLICY(cache_policy == L2_STREAM);
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}
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if (flags & CP_DMA_CLEAR)
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if (flags & CP_DMA_CLEAR) {
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header |= S_411_SRC_SEL(V_411_DATA);
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else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS)
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header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
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} else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS) {
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header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
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S_500_SRC_CACHE_POLICY(cache_policy == L2_STREAM);
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}
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if (sctx->chip_class >= CIK) {
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radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
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@ -1111,6 +1111,7 @@ void si_init_clear_functions(struct si_context *sctx);
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enum si_cache_policy {
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L2_BYPASS,
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L2_LRU, /* same as SLC=0 */
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L2_STREAM, /* same as SLC=1 */
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};
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enum si_coherency {
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