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aco: fix >8 byte linear vgpr copies

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No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27436>
(cherry picked from commit 174e37afb9ebcd556bc18555ca2aa3276b3d8e04)
This commit is contained in:
Rhys Perry 2024-02-02 12:00:31 +00:00 • committed by Eric Engestrom
parent 71c1740914
commit 223c8cd0d3
3 changed files with 31 additions and 7 deletions
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2
.pick_status.json
View file

@ -284,7 +284,7 @@
"description": "aco: fix >8 byte linear vgpr copies", "description": "aco: fix >8 byte linear vgpr copies",
"nominated": true, "nominated": true,
"nomination_type": 0, "nomination_type": 0,
"resolution": 0, "resolution": 1,
"main_sha": null, "main_sha": null,
"because_sha": null, "because_sha": null,
"notes": null "notes": null

10
src/amd/compiler/aco_lower_to_hw_instr.cpp
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@ -1820,17 +1820,15 @@ handle_operands(std::map<PhysReg, copy_operation>& copy_map, lower_context* ctx,
if (it->second.bytes > 8) { if (it->second.bytes > 8) {
assert(!it->second.op.isConstant()); assert(!it->second.op.isConstant());
assert(!it->second.def.regClass().is_subdword()); assert(!it->second.def.regClass().is_subdword());
RegClass rc = RegClass(it->second.def.regClass().type(), it->second.def.size() - 2); RegClass rc = it->second.def.regClass().resize(it->second.def.bytes() - 8);
Definition hi_def = Definition(PhysReg{it->first + 2}, rc); Definition hi_def = Definition(PhysReg{it->first + 2}, rc);
rc = RegClass(it->second.op.regClass().type(), it->second.op.size() - 2); rc = it->second.op.regClass().resize(it->second.op.bytes() - 8);
Operand hi_op = Operand(PhysReg{it->second.op.physReg() + 2}, rc); Operand hi_op = Operand(PhysReg{it->second.op.physReg() + 2}, rc);
copy_operation copy = {hi_op, hi_def, it->second.bytes - 8}; copy_operation copy = {hi_op, hi_def, it->second.bytes - 8};
copy_map[hi_def.physReg()] = copy; copy_map[hi_def.physReg()] = copy;
assert(it->second.op.physReg().byte() == 0 && it->second.def.physReg().byte() == 0); assert(it->second.op.physReg().byte() == 0 && it->second.def.physReg().byte() == 0);
it->second.op = Operand(it->second.op.physReg(), it->second.op = Operand(it->second.op.physReg(), it->second.op.regClass().resize(8));
it->second.op.regClass().type() == RegType::sgpr ? s2 : v2); it->second.def = Definition(it->second.def.physReg(), it->second.def.regClass().resize(8));
it->second.def = Definition(it->second.def.physReg(),
it->second.def.regClass().type() == RegType::sgpr ? s2 : v2);
it->second.bytes = 8; it->second.bytes = 8;
} }

26
src/amd/compiler/tests/test_to_hw_instr.cpp
View file

@ -809,6 +809,32 @@ BEGIN_TEST(to_hw_instr.swap_linear_vgpr)
finish_to_hw_instr_test(); finish_to_hw_instr_test();
END_TEST END_TEST
BEGIN_TEST(to_hw_instr.copy_linear_vgpr_v3)
if (!setup_cs(NULL, GFX10))
return;
PhysReg reg_v0{256};
PhysReg reg_v4{256 + 4};
RegClass v3_linear = v3.as_linear();
//>> p_unit_test 0
bld.pseudo(aco_opcode::p_unit_test, Operand::zero());
//! lv2: %0:v[0-1] = v_lshrrev_b64 0, %0:v[4-5]
//! s2: %0:exec, s1: %0:scc = s_not_b64 %0:exec
//! lv2: %0:v[0-1] = v_lshrrev_b64 0, %0:v[4-5]
//! s2: %0:exec, s1: %0:scc = s_not_b64 %0:exec
//! lv1: %0:v[2] = v_mov_b32 %0:v[6]
//! s2: %0:exec, s1: %0:scc = s_not_b64 %0:exec
//! lv1: %0:v[2] = v_mov_b32 %0:v[6]
//! s2: %0:exec, s1: %0:scc = s_not_b64 %0:exec
Instruction* instr = bld.pseudo(aco_opcode::p_parallelcopy, Definition(reg_v0, v3_linear),
Operand(reg_v4, v3_linear));
instr->pseudo().scratch_sgpr = m0;
finish_to_hw_instr_test();
END_TEST
BEGIN_TEST(to_hw_instr.pack2x16_constant) BEGIN_TEST(to_hw_instr.pack2x16_constant)
PhysReg v0_lo{256}; PhysReg v0_lo{256};
PhysReg v0_hi{256}; PhysReg v0_hi{256};