diff --git a/src/asahi/lib/agx_meta.c b/src/asahi/lib/agx_meta.c
index e0b90ad7fff..1d5c3444627 100644
--- a/src/asahi/lib/agx_meta.c
+++ b/src/asahi/lib/agx_meta.c
@@ -92,7 +92,7 @@ build_background_op(nir_builder *b, enum agx_meta_op op, unsigned rt,
       }
 
       tex->coord_components = layered ? 3 : 2;
-      tex->texture_index = rt;
+      tex->texture_index = rt * 2;
       nir_def_init(&tex->instr, &tex->def, 4, 32);
       nir_builder_instr_insert(b, &tex->instr);
 
diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c
index 04c91239625..4c90e25f72c 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -2779,6 +2779,10 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render)
    /* Construct the key */
    struct agx_meta_key key = {.tib = batch->tilebuffer_layout};
 
+   bool needs_textures_for_spilled_rts =
+      agx_tilebuffer_spills(&batch->tilebuffer_layout) && !partial_render &&
+      !store;
+
    for (unsigned rt = 0; rt < PIPE_MAX_COLOR_BUFS; ++rt) {
       struct pipe_surface *surf = batch->key.cbufs[rt];
 
@@ -2824,6 +2828,12 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render)
    for (unsigned rt = 0; rt < PIPE_MAX_COLOR_BUFS; ++rt) {
       if (key.op[rt] == AGX_META_OP_LOAD) {
          /* Each reloaded render target is textured */
+         needs_sampler = true;
+
+         /* Will be uploaded later, this would be clobbered */
+         if (needs_textures_for_spilled_rts)
+            continue;
+
          struct agx_ptr texture =
             agx_pool_alloc_aligned(&batch->pool, AGX_TEXTURE_LENGTH, 64);
          struct pipe_surface *surf = batch->key.cbufs[rt];
@@ -2835,12 +2845,12 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render)
          agx_pack_texture(texture.cpu, rsrc, surf->format, &sampler_view);
 
          agx_usc_pack(&b, TEXTURE, cfg) {
-            cfg.start = rt;
+            /* Shifted to match eMRT indexing, could be optimized */
+            cfg.start = rt * 2;
             cfg.count = 1;
             cfg.buffer = texture.gpu;
          }
 
-         needs_sampler = true;
       } else if (key.op[rt] == AGX_META_OP_CLEAR) {
          assert(batch->uploaded_clear_color[rt] && "set when cleared");
          agx_usc_uniform(&b, 4 + (8 * rt), 8, batch->uploaded_clear_color[rt]);
@@ -2864,8 +2874,7 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render)
       }
    }
 
-   if (agx_tilebuffer_spills(&batch->tilebuffer_layout) && !partial_render &&
-       !store) {
+   if (needs_textures_for_spilled_rts) {
       /* Upload texture/PBE descriptors for each render target so we can clear
        * spilled render targets.
        */