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anv: cleanup, use intel_needs_workaround instead of is_dg2

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Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26666>
This commit is contained in:
Tapani Pälli 2023-12-13 13:40:17 +02:00 • committed by Marge Bot
parent 012b6fbe63
commit 2f25679b3f
1 changed files with 4 additions and 4 deletions
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8
src/intel/vulkan/genX_pipeline.c
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@ -1918,16 +1918,16 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
#endif
#if GFX_VERx10 >= 125
struct anv_device *device = pipeline->base.base.device;
anv_pipeline_emit(pipeline, partial.vfg, GENX(3DSTATE_VFG), vfg) {
/* If 3DSTATE_TE: TE Enable == 1 then RR_STRICT else RR_FREE*/
vfg.DistributionMode =
anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL) ? RR_STRICT :
RR_FREE;
vfg.DistributionGranularity = BatchLevelGranularity;
/* Wa_14014890652 */
if (intel_device_info_is_dg2(device->info))
vfg.GranularityThresholdDisable = 1;
#if INTEL_WA_14014851047_GFX_VER
vfg.GranularityThresholdDisable =
intel_needs_workaround(pipeline->base.base.device->info, 14014851047);
#endif
/* 192 vertices for TRILIST_ADJ */
vfg.ListNBatchSizeScale = 0;
/* Batch size of 384 vertices */