From 395dee0d89b82facdb63a510bd373656c4f9db3e Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 2 Jan 2024 15:42:02 +0100 Subject: [PATCH] radv: drop si_ prefix from all functions Most of these functions were copied from RadeonSI but they should be prefixed with radv_ instead. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/meta/radv_meta_buffer.c | 6 +- src/amd/vulkan/meta/radv_meta_fast_clear.c | 6 +- src/amd/vulkan/radv_cmd_buffer.c | 150 ++++++++++----------- src/amd/vulkan/radv_debug.c | 6 +- src/amd/vulkan/radv_device.c | 6 +- src/amd/vulkan/radv_image.c | 10 +- src/amd/vulkan/radv_image_view.c | 20 +-- src/amd/vulkan/radv_perfcounter.c | 6 +- src/amd/vulkan/radv_pipeline_graphics.c | 35 ++--- src/amd/vulkan/radv_private.h | 87 ++++++------ src/amd/vulkan/radv_query.c | 20 +-- src/amd/vulkan/radv_queue.c | 12 +- src/amd/vulkan/radv_sqtt.c | 2 +- src/amd/vulkan/radv_video.c | 4 +- src/amd/vulkan/si_cmd_buffer.c | 146 ++++++++++---------- 15 files changed, 259 insertions(+), 257 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta_buffer.c b/src/amd/vulkan/meta/radv_meta_buffer.c index 79aa49bf78b..01aa9cb2629 100644 --- a/src/amd/vulkan/meta/radv_meta_buffer.c +++ b/src/amd/vulkan/meta/radv_meta_buffer.c @@ -248,7 +248,7 @@ radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE | radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image); } else if (size) - si_cp_dma_clear_buffer(cmd_buffer, va, size, value); + radv_cp_dma_clear_buffer(cmd_buffer, va, size, value); return flush_bits; } @@ -271,7 +271,7 @@ radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *sr else if (use_compute) copy_buffer_shader(cmd_buffer, src_va, dst_va, size); else if (size) - si_cp_dma_buffer_copy(cmd_buffer, src_va, dst_va, size); + radv_cp_dma_buffer_copy(cmd_buffer, src_va, dst_va, size); } VKAPI_ATTR void VKAPI_CALL @@ -326,7 +326,7 @@ radv_update_buffer_cp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, const voi assert(size < RADV_BUFFER_UPDATE_THRESHOLD); - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, words + 4); radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + words, 0)); diff --git a/src/amd/vulkan/meta/radv_meta_fast_clear.c b/src/amd/vulkan/meta/radv_meta_fast_clear.c index 8af0aebceb1..e6a0361688d 100644 --- a/src/amd/vulkan/meta/radv_meta_fast_clear.c +++ b/src/amd/vulkan/meta/radv_meta_fast_clear.c @@ -452,7 +452,7 @@ radv_emit_set_predication_state_from_image(struct radv_cmd_buffer *cmd_buffer, s va += pred_offset; } - si_emit_set_predication_state(cmd_buffer, true, PREDICATION_OP_BOOL64, va); + radv_emit_set_predication_state(cmd_buffer, true, PREDICATION_OP_BOOL64, va); } static void @@ -617,8 +617,8 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image * if (cmd_buffer->state.predication_type != -1) { /* Restore previous conditional rendering user state. */ - si_emit_set_predication_state(cmd_buffer, cmd_buffer->state.predication_type, cmd_buffer->state.predication_op, - cmd_buffer->state.predication_va); + radv_emit_set_predication_state(cmd_buffer, cmd_buffer->state.predication_type, + cmd_buffer->state.predication_op, cmd_buffer->state.predication_va); } } diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 95d3d3339ee..dab2230d778 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -630,8 +630,8 @@ radv_gang_cache_flush(struct radv_cmd_buffer *cmd_buffer) const uint32_t flush_bits = cmd_buffer->gang.flush_bits; enum rgp_flush_bits sqtt_flush_bits = 0; - si_cs_emit_cache_flush(cmd_buffer->device->ws, ace_cs, cmd_buffer->device->physical_device->rad_info.gfx_level, NULL, - 0, RADV_QUEUE_COMPUTE, flush_bits, &sqtt_flush_bits, 0); + radv_cs_emit_cache_flush(cmd_buffer->device->ws, ace_cs, cmd_buffer->device->physical_device->rad_info.gfx_level, + NULL, 0, RADV_QUEUE_COMPUTE, flush_bits, &sqtt_flush_bits, 0); cmd_buffer->gang.flush_bits = 0; } @@ -677,9 +677,9 @@ radv_flush_gang_semaphore(struct radv_cmd_buffer *cmd_buffer, struct radeon_cmdb ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12); - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, qf, - V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, - cmd_buffer->gang.sem.va + va_off, value, cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, qf, + V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, + cmd_buffer->gang.sem.va + va_off, value, cmd_buffer->gfx9_eop_bug_va); assert(cmd_buffer->cs->cdw <= cdw_max); return true; @@ -794,14 +794,14 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flu assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH)); /* Force wait for graphics or compute engines to be idle. */ - si_cs_emit_cache_flush(device->ws, cmd_buffer->cs, device->physical_device->rad_info.gfx_level, - &cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va, cmd_buffer->qf, flags, - &sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_cache_flush(device->ws, cmd_buffer->cs, device->physical_device->rad_info.gfx_level, + &cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va, cmd_buffer->qf, flags, + &sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va); if ((flags & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) && radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TASK)) { /* Force wait for compute engines to be idle on the internal cmdbuf. */ - si_cs_emit_cache_flush(device->ws, cmd_buffer->gang.cs, device->physical_device->rad_info.gfx_level, NULL, 0, - RADV_QUEUE_COMPUTE, RADV_CMD_FLAG_CS_PARTIAL_FLUSH, &sqtt_flush_bits, 0); + radv_cs_emit_cache_flush(device->ws, cmd_buffer->gang.cs, device->physical_device->rad_info.gfx_level, NULL, 0, + RADV_QUEUE_COMPUTE, RADV_CMD_FLAG_CS_PARTIAL_FLUSH, &sqtt_flush_bits, 0); } } @@ -976,7 +976,7 @@ radv_get_rasterization_prim(struct radv_cmd_buffer *cmd_buffer) return cmd_buffer->state.rast_prim; } - return si_conv_prim_to_gs_out(d->vk.ia.primitive_topology, last_vgt_shader->info.is_ngg); + return radv_conv_prim_to_gs_out(d->vk.ia.primitive_topology, last_vgt_shader->info.is_ngg); } static ALWAYS_INLINE unsigned @@ -1644,7 +1644,7 @@ radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer, struct radv_shader va = radv_shader_get_va(shader); - si_cp_dma_prefetch(cmd_buffer, va, shader->code_size); + radv_cp_dma_prefetch(cmd_buffer, va, shader->code_size); } ALWAYS_INLINE static void @@ -1664,7 +1664,7 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer, bool first_stage_only) radv_emit_shader_prefetch(cmd_buffer, cmd_buffer->state.shaders[MESA_SHADER_MESH]); if (mask & RADV_PREFETCH_VBO_DESCRIPTORS) - si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size); + radv_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size); if (mask & RADV_PREFETCH_TCS) radv_emit_shader_prefetch(cmd_buffer, cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL]); @@ -2100,7 +2100,7 @@ radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer) { const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; - si_write_scissors(cmd_buffer->cs, d->vk.vp.scissor_count, d->vk.vp.scissors, d->vk.vp.viewports); + radv_write_scissors(cmd_buffer->cs, d->vk.vp.scissor_count, d->vk.vp.scissors, d->vk.vp.viewports); } static void @@ -2290,7 +2290,7 @@ radv_emit_provoking_vertex_mode(struct radv_cmd_buffer *cmd_buffer) if (d->vk.rs.provoking_vertex == VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT) { if (stage == MESA_SHADER_VERTEX) { - provoking_vtx = si_conv_prim_to_gs_out(d->vk.ia.primitive_topology, last_vgt_shader->info.is_ngg); + provoking_vtx = radv_conv_prim_to_gs_out(d->vk.ia.primitive_topology, last_vgt_shader->info.is_ngg); } else { assert(stage == MESA_SHADER_GEOMETRY); provoking_vtx = last_vgt_shader->info.gs.vertices_in - 1; @@ -2323,7 +2323,7 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer) base_reg = last_vgt_shader->info.user_data_0; radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, - si_conv_prim_to_gs_out(d->vk.ia.primitive_topology, last_vgt_shader->info.is_ngg) + 1); + radv_conv_prim_to_gs_out(d->vk.ia.primitive_topology, last_vgt_shader->info.is_ngg) + 1); } static void @@ -2350,12 +2350,12 @@ radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer) const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, - S_02842C_STENCILFAIL(si_translate_stencil_op(d->vk.ds.stencil.front.op.fail)) | - S_02842C_STENCILZPASS(si_translate_stencil_op(d->vk.ds.stencil.front.op.pass)) | - S_02842C_STENCILZFAIL(si_translate_stencil_op(d->vk.ds.stencil.front.op.depth_fail)) | - S_02842C_STENCILFAIL_BF(si_translate_stencil_op(d->vk.ds.stencil.back.op.fail)) | - S_02842C_STENCILZPASS_BF(si_translate_stencil_op(d->vk.ds.stencil.back.op.pass)) | - S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(d->vk.ds.stencil.back.op.depth_fail))); + S_02842C_STENCILFAIL(radv_translate_stencil_op(d->vk.ds.stencil.front.op.fail)) | + S_02842C_STENCILZPASS(radv_translate_stencil_op(d->vk.ds.stencil.front.op.pass)) | + S_02842C_STENCILZFAIL(radv_translate_stencil_op(d->vk.ds.stencil.front.op.depth_fail)) | + S_02842C_STENCILFAIL_BF(radv_translate_stencil_op(d->vk.ds.stencil.back.op.fail)) | + S_02842C_STENCILZPASS_BF(radv_translate_stencil_op(d->vk.ds.stencil.back.op.pass)) | + S_02842C_STENCILZFAIL_BF(radv_translate_stencil_op(d->vk.ds.stencil.back.op.depth_fail))); } static bool @@ -3678,8 +3678,8 @@ radv_emit_guardband_state(struct radv_cmd_buffer *cmd_buffer) const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; unsigned rast_prim = radv_get_rasterization_prim(cmd_buffer); - si_write_guardband(cmd_buffer->cs, d->vk.vp.viewport_count, d->vk.vp.viewports, rast_prim, d->vk.rs.polygon_mode, - d->vk.rs.line.width); + radv_write_guardband(cmd_buffer->cs, d->vk.vp.viewport_count, d->vk.vp.viewports, rast_prim, d->vk.rs.polygon_mode, + d->vk.rs.line.width); cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_GUARDBAND; } @@ -4133,22 +4133,22 @@ radv_emit_color_blend(struct radv_cmd_buffer *cmd_buffer) * First, get rid of DST in the blend factors: * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC) */ - si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, VK_BLEND_FACTOR_DST_COLOR, VK_BLEND_FACTOR_SRC_COLOR); + radv_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, VK_BLEND_FACTOR_DST_COLOR, VK_BLEND_FACTOR_SRC_COLOR); - si_blend_remove_dst(&eqA, &srcA, &dstA, VK_BLEND_FACTOR_DST_COLOR, VK_BLEND_FACTOR_SRC_COLOR); + radv_blend_remove_dst(&eqA, &srcA, &dstA, VK_BLEND_FACTOR_DST_COLOR, VK_BLEND_FACTOR_SRC_COLOR); - si_blend_remove_dst(&eqA, &srcA, &dstA, VK_BLEND_FACTOR_DST_ALPHA, VK_BLEND_FACTOR_SRC_ALPHA); + radv_blend_remove_dst(&eqA, &srcA, &dstA, VK_BLEND_FACTOR_DST_ALPHA, VK_BLEND_FACTOR_SRC_ALPHA); /* Look up the ideal settings from tables. */ - srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false); - dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false); - srcA_opt = si_translate_blend_opt_factor(srcA, true); - dstA_opt = si_translate_blend_opt_factor(dstA, true); + srcRGB_opt = radv_translate_blend_opt_factor(srcRGB, false); + dstRGB_opt = radv_translate_blend_opt_factor(dstRGB, false); + srcA_opt = radv_translate_blend_opt_factor(srcA, true); + dstA_opt = radv_translate_blend_opt_factor(dstA, true); /* Handle interdependencies. */ - if (si_blend_factor_uses_dst(srcRGB)) + if (radv_blend_factor_uses_dst(srcRGB)) dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; - if (si_blend_factor_uses_dst(srcA)) + if (radv_blend_factor_uses_dst(srcA)) dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE && @@ -4158,19 +4158,19 @@ radv_emit_color_blend(struct radv_cmd_buffer *cmd_buffer) /* Set the final value. */ sx_mrt_blend_opt[i] = S_028760_COLOR_SRC_OPT(srcRGB_opt) | S_028760_COLOR_DST_OPT(dstRGB_opt) | - S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) | + S_028760_COLOR_COMB_FCN(radv_translate_blend_opt_function(eqRGB)) | S_028760_ALPHA_SRC_OPT(srcA_opt) | S_028760_ALPHA_DST_OPT(dstA_opt) | - S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA)); + S_028760_ALPHA_COMB_FCN(radv_translate_blend_opt_function(eqA)); blend_cntl |= S_028780_ENABLE(1); - blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); - blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(gfx_level, srcRGB)); - blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(gfx_level, dstRGB)); + blend_cntl |= S_028780_COLOR_COMB_FCN(radv_translate_blend_function(eqRGB)); + blend_cntl |= S_028780_COLOR_SRCBLEND(radv_translate_blend_factor(gfx_level, srcRGB)); + blend_cntl |= S_028780_COLOR_DESTBLEND(radv_translate_blend_factor(gfx_level, dstRGB)); if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); - blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); - blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(gfx_level, srcA)); - blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(gfx_level, dstA)); + blend_cntl |= S_028780_ALPHA_COMB_FCN(radv_translate_blend_function(eqA)); + blend_cntl |= S_028780_ALPHA_SRCBLEND(radv_translate_blend_factor(gfx_level, srcA)); + blend_cntl |= S_028780_ALPHA_DESTBLEND(radv_translate_blend_factor(gfx_level, dstA)); } cb_blend_control[i] = blend_cntl; } @@ -5218,8 +5218,8 @@ struct radv_draw_info { }; static void -si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw, bool indirect_draw, - bool count_from_stream_output, uint32_t draw_vertex_count) +radv_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw, bool indirect_draw, + bool count_from_stream_output, uint32_t draw_vertex_count) { const struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info; struct radv_cmd_state *state = &cmd_buffer->state; @@ -5229,9 +5229,9 @@ si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dr struct radeon_cmdbuf *cs = cmd_buffer->cs; unsigned ia_multi_vgt_param; - ia_multi_vgt_param = - si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, count_from_stream_output, draw_vertex_count, - topology, prim_restart_enable, patch_control_points, state->tess_num_patches); + ia_multi_vgt_param = radv_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, count_from_stream_output, + draw_vertex_count, topology, prim_restart_enable, + patch_control_points, state->tess_num_patches); if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) { if (info->gfx_level == GFX9) { @@ -5295,8 +5295,8 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_d if (info->gfx_level >= GFX10) { gfx10_emit_ge_cntl(cmd_buffer); } else { - si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1, draw_info->indirect, - !!draw_info->strmout_buffer, draw_info->indirect ? 0 : draw_info->count); + radv_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1, draw_info->indirect, + !!draw_info->strmout_buffer, draw_info->indirect ? 0 : draw_info->count); } /* RDNA2 is affected by a hardware bug when instance packing is enabled for adjacent primitive @@ -6223,12 +6223,12 @@ radv_EndCommandBuffer(VkCommandBuffer commandBuffer) } if (is_gfx_or_ace) { - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); /* Make sure CP DMA is idle at the end of IBs because the kernel * doesn't wait for it. */ - si_cp_dma_wait_for_idle(cmd_buffer); + radv_cp_dma_wait_for_idle(cmd_buffer); } radv_describe_end_cmd_buffer(cmd_buffer); @@ -6889,7 +6889,7 @@ radv_CmdSetPrimitiveTopology(VkCommandBuffer commandBuffer, VkPrimitiveTopology { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); struct radv_cmd_state *state = &cmd_buffer->state; - unsigned primitive_topology = si_translate_prim(primitiveTopology); + unsigned primitive_topology = radv_translate_prim(primitiveTopology); if (radv_primitive_topology_is_line_list(state->dynamic.vk.ia.primitive_topology) != radv_primitive_topology_is_line_list(primitive_topology)) @@ -7059,7 +7059,7 @@ radv_CmdSetLogicOpEXT(VkCommandBuffer commandBuffer, VkLogicOp logicOp) { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); struct radv_cmd_state *state = &cmd_buffer->state; - unsigned logic_op = si_translate_blend_logic_op(logicOp); + unsigned logic_op = radv_translate_blend_logic_op(logicOp); state->dynamic.vk.cb.logic_op = logic_op; @@ -7172,7 +7172,7 @@ radv_CmdSetPolygonModeEXT(VkCommandBuffer commandBuffer, VkPolygonMode polygonMo { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); struct radv_cmd_state *state = &cmd_buffer->state; - unsigned polygon_mode = si_translate_fill(polygonMode); + unsigned polygon_mode = radv_translate_fill(polygonMode); if (radv_polygon_mode_is_points_or_lines(state->dynamic.vk.rs.polygon_mode) != radv_polygon_mode_is_points_or_lines(polygon_mode)) @@ -7450,10 +7450,10 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou radv_emit_mip_change_flush_default(primary); /* Emit pending flushes on primary prior to executing secondary */ - si_emit_cache_flush(primary); + radv_emit_cache_flush(primary); /* Make sure CP DMA is idle on primary prior to executing secondary. */ - si_cp_dma_wait_for_idle(primary); + radv_cp_dma_wait_for_idle(primary); for (uint32_t i = 0; i < commandBufferCount; i++) { RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]); @@ -8743,7 +8743,7 @@ radv_get_ngg_culling_settings(struct radv_cmd_buffer *cmd_buffer, bool vp_y_inve * because we don't know the primitive topology at compile time, so we should * disable it dynamically for points or lines. */ - const unsigned num_vertices_per_prim = si_conv_prim_to_gs_out(d->vk.ia.primitive_topology, true) + 1; + const unsigned num_vertices_per_prim = radv_conv_prim_to_gs_out(d->vk.ia.primitive_topology, true) + 1; if (num_vertices_per_prim != 3) return radv_nggc_none; @@ -9077,7 +9077,7 @@ radv_before_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info * packets between the wait and the draw) */ radv_emit_all_graphics_states(cmd_buffer, info); - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); /* <-- CUs are idle here --> */ radv_upload_graphics_shader_descriptors(cmd_buffer); @@ -9087,7 +9087,7 @@ radv_before_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info /* If we don't wait for idle, start prefetches first, then set * states, and draw at the end. */ - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); if (need_prefetch) { /* Only prefetch the vertex shader and VBO descriptors @@ -9144,7 +9144,7 @@ radv_before_taskmesh_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_ radv_emit_all_graphics_states(cmd_buffer, info); - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); if (task_shader) { radv_gang_cache_flush(cmd_buffer); @@ -9798,7 +9798,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf * packets between the wait and the draw) */ radv_emit_compute_pipeline(cmd_buffer, pipeline); - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); /* <-- CUs are idle here --> */ radv_upload_compute_shader_descriptors(cmd_buffer, bind_point); @@ -9817,7 +9817,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf /* If we don't wait for idle, start prefetches first, then set * states, and dispatch at the end. */ - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); if (has_prefetch && pipeline_is_dirty) { radv_emit_shader_prefetch(cmd_buffer, compute_shader); @@ -9863,7 +9863,7 @@ radv_dgc_before_dispatch(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH; radv_emit_compute_pipeline(cmd_buffer, pipeline); - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); radv_upload_compute_shader_descriptors(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE); @@ -10458,7 +10458,7 @@ radv_cp_dma_wait_for_stages(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageF if (stage_mask & (VK_PIPELINE_STAGE_2_COPY_BIT | VK_PIPELINE_STAGE_2_CLEAR_BIT | VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)) - si_cp_dma_wait_for_idle(cmd_buffer); + radv_cp_dma_wait_for_idle(cmd_buffer); } static void @@ -10572,7 +10572,7 @@ write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event, VkPipe if (cmd_buffer->qf == RADV_QUEUE_VIDEO_DEC) return; - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo); @@ -10625,9 +10625,9 @@ write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event, VkPipe event_type = V_028A90_BOTTOM_OF_PIPE_TS; } - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, - event_type, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, va, value, - cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, + event_type, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, va, value, + cmd_buffer->gfx9_eop_bug_va); } assert(cmd_buffer->cs->cdw <= cdw_max); @@ -10690,7 +10690,7 @@ radv_begin_conditional_rendering(struct radv_cmd_buffer *cmd_buffer, uint64_t va struct radeon_cmdbuf *cs = cmd_buffer->cs; unsigned pred_op = PREDICATION_OP_BOOL32; - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); if (cmd_buffer->qf == RADV_QUEUE_GENERAL && !cmd_buffer->device->physical_device->rad_info.has_32bit_predication) { uint64_t pred_value = 0, pred_va; @@ -10745,7 +10745,7 @@ radv_begin_conditional_rendering(struct radv_cmd_buffer *cmd_buffer, uint64_t va /* MEC doesn't support predication, we emulate it elsewhere. */ if (!radv_cmd_buffer_uses_mec(cmd_buffer)) { - si_emit_set_predication_state(cmd_buffer, draw_visible, pred_op, va); + radv_emit_set_predication_state(cmd_buffer, draw_visible, pred_op, va); } } @@ -10754,7 +10754,7 @@ radv_end_conditional_rendering(struct radv_cmd_buffer *cmd_buffer) { /* MEC doesn't support predication, no need to emit anything here. */ if (!radv_cmd_buffer_uses_mec(cmd_buffer)) { - si_emit_set_predication_state(cmd_buffer, false, 0, 0); + radv_emit_set_predication_state(cmd_buffer, false, 0, 0); } } @@ -11028,7 +11028,7 @@ radv_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCou if (cmd_buffer->device->physical_device->use_ngg_streamout) { /* Wait for streamout to finish before reading GDS_STRMOUT registers. */ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH; - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); } else { radv_flush_vgt_streamout(cmd_buffer); } @@ -11174,7 +11174,7 @@ radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlag return; } - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12); @@ -11186,9 +11186,9 @@ radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlag radeon_emit(cs, va); radeon_emit(cs, va >> 32); } else { - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, - V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, va, marker, - cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, + V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, va, marker, + cmd_buffer->gfx9_eop_bug_va); } assert(cmd_buffer->cs->cdw <= cdw_max); diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c index 76ba55c4de2..6cdc1b79500 100644 --- a/src/amd/vulkan/radv_debug.c +++ b/src/amd/vulkan/radv_debug.c @@ -259,7 +259,7 @@ struct radv_shader_inst { /* Split a disassembly string into lines and add them to the array pointed * to by "instructions". */ static void -si_add_split_disasm(const char *disasm, uint64_t start_addr, unsigned *num, struct radv_shader_inst *instructions) +radv_add_split_disasm(const char *disasm, uint64_t start_addr, unsigned *num, struct radv_shader_inst *instructions) { struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL; char *next; @@ -325,7 +325,7 @@ radv_dump_annotated_shader(const struct radv_shader *shader, gl_shader_stage sta unsigned num_inst = 0; struct radv_shader_inst *instructions = calloc(shader->code_size / 4, sizeof(struct radv_shader_inst)); - si_add_split_disasm(shader->disasm_string, start_addr, &num_inst, instructions); + radv_add_split_disasm(shader->disasm_string, start_addr, &num_inst, instructions); fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n", radv_get_shader_name(&shader->info, stage)); @@ -970,7 +970,7 @@ radv_dump_faulty_shader(struct radv_device *device, uint64_t faulty_pc) struct radv_shader_inst *instructions = calloc(shader->code_size / 4, sizeof(struct radv_shader_inst)); /* Split the disassembly string into instructions. */ - si_add_split_disasm(shader->disasm_string, start_addr, &num_inst, instructions); + radv_add_split_disasm(shader->disasm_string, start_addr, &num_inst, instructions); /* Print instructions with annotations. */ for (unsigned i = 0; i < num_inst; i++) { diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 9d2111f4263..e582c709ade 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -1561,7 +1561,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff pitch_tile_max = level_info->nblk_x / 8 - 1; slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1; - tile_mode_index = si_tile_mode_index(plane, iview->vk.base_mip_level, false); + tile_mode_index = radv_tile_mode_index(plane, iview->vk.base_mip_level, false); cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max); cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max); @@ -1937,9 +1937,9 @@ radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buff ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode)); ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode)); } else { - unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false); + unsigned tile_mode_index = radv_tile_mode_index(&iview->image->planes[0], level, false); ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); - tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true); + tile_mode_index = radv_tile_mode_index(&iview->image->planes[0], level, true); ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); if (stencil_only) ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index c15aefc8fdf..804fbf0f0cd 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -426,7 +426,7 @@ radv_use_tc_compat_cmask_for_image(struct radv_device *device, struct radv_image } static uint32_t -si_get_bo_metadata_word1(const struct radv_device *device) +radv_get_bo_metadata_word1(const struct radv_device *device) { return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id; } @@ -434,7 +434,7 @@ si_get_bo_metadata_word1(const struct radv_device *device) static bool radv_is_valid_opaque_metadata(const struct radv_device *device, const struct radeon_bo_metadata *md) { - if (md->metadata[0] != 1 || md->metadata[1] != si_get_bo_metadata_word1(device)) + if (md->metadata[0] != 1 || md->metadata[1] != radv_get_bo_metadata_word1(device)) return false; if (md->size_metadata < 40) @@ -749,8 +749,8 @@ radv_query_opaque_metadata(struct radv_device *device, struct radv_image *image, &fixedmapping, 0, image->vk.mip_levels - 1, 0, image->vk.array_layers - 1, plane_width, plane_height, image->vk.extent.depth, 0.0f, desc, NULL, 0, NULL, NULL); - si_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, 0, 0, surface->blk_w, false, false, false, - false, desc, NULL); + radv_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, 0, 0, surface->blk_w, false, false, false, + false, desc, NULL); ac_surface_compute_umd_metadata(&device->physical_device->rad_info, surface, image->vk.mip_levels, desc, &md->size_metadata, md->metadata, @@ -1547,7 +1547,7 @@ radv_image_is_renderable(const struct radv_device *device, const struct radv_ima } unsigned -si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil) +radv_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil) { if (stencil) return plane->surface.u.legacy.zs.stencil_tiling_index[level]; diff --git a/src/amd/vulkan/radv_image_view.c b/src/amd/vulkan/radv_image_view.c index af0695da7d5..22a55c88aca 100644 --- a/src/amd/vulkan/radv_image_view.c +++ b/src/amd/vulkan/radv_image_view.c @@ -94,11 +94,11 @@ radv_tex_dim(VkImageType image_type, VkImageViewType view_type, unsigned nr_laye } void -si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *image, - const struct legacy_surf_level *base_level_info, unsigned plane_id, unsigned base_level, - unsigned first_level, unsigned block_width, bool is_stencil, bool is_storage_image, - bool disable_compression, bool enable_write_compression, uint32_t *state, - const struct ac_surf_nbc_view *nbc_view) +radv_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *image, + const struct legacy_surf_level *base_level_info, unsigned plane_id, + unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil, + bool is_storage_image, bool disable_compression, bool enable_write_compression, + uint32_t *state, const struct ac_surf_nbc_view *nbc_view) { struct radv_image_plane *plane = &image->planes[plane_id]; struct radv_image_binding *binding = image->disjoint ? &image->bindings[plane_id] : &image->bindings[0]; @@ -224,7 +224,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im } else { /* GFX6-GFX8 */ unsigned pitch = base_level_info->nblk_x * block_width; - unsigned index = si_tile_mode_index(plane, base_level, is_stencil); + unsigned index = radv_tile_mode_index(plane, base_level, is_stencil); state[3] &= C_008F1C_TILING_INDEX; state[3] |= S_008F1C_TILING_INDEX(index); @@ -696,10 +696,10 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic bool enable_write_compression = radv_image_use_dcc_image_stores(device, image); if (is_storage_image && !(enable_write_compression || enable_compression)) disable_compression = true; - si_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, iview->vk.base_mip_level, - iview->vk.base_mip_level, blk_w, is_stencil, is_storage_image, disable_compression, - enable_write_compression, descriptor->plane_descriptors[descriptor_plane_id], - nbc_view); + radv_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, iview->vk.base_mip_level, + iview->vk.base_mip_level, blk_w, is_stencil, is_storage_image, disable_compression, + enable_write_compression, descriptor->plane_descriptors[descriptor_plane_id], + nbc_view); } /** diff --git a/src/amd/vulkan/radv_perfcounter.c b/src/amd/vulkan/radv_perfcounter.c index e24a7af20f6..a8d27483e68 100644 --- a/src/amd/vulkan/radv_perfcounter.c +++ b/src/amd/vulkan/radv_perfcounter.c @@ -710,9 +710,9 @@ radv_pc_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_pc_query_pool radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->device->perf_counter_bo); uint64_t perf_ctr_va = radv_buffer_get_va(cmd_buffer->device->perf_counter_bo) + PERF_CTR_BO_FENCE_OFFSET; - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, - V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, perf_ctr_va, 1, - cmd_buffer->gfx9_fence_va); + radv_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, + V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, perf_ctr_va, + 1, cmd_buffer->gfx9_fence_va); radv_cp_wait_mem(cs, cmd_buffer->qf, WAIT_REG_MEM_EQUAL, perf_ctr_va, 1, 0xffffffff); radv_pc_wait_idle(cmd_buffer); diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index c52a42b2196..bc693edbf97 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -123,8 +123,8 @@ radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline) * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC) */ void -si_blend_remove_dst(VkBlendOp *func, VkBlendFactor *src_factor, VkBlendFactor *dst_factor, VkBlendFactor expected_dst, - VkBlendFactor replacement_src) +radv_blend_remove_dst(VkBlendOp *func, VkBlendFactor *src_factor, VkBlendFactor *dst_factor, VkBlendFactor expected_dst, + VkBlendFactor replacement_src) { if (*src_factor == expected_dst && *dst_factor == VK_BLEND_FACTOR_ZERO) { *src_factor = VK_BLEND_FACTOR_ZERO; @@ -339,7 +339,7 @@ radv_pipeline_init_multisample_state(const struct radv_device *device, struct ra } static uint32_t -si_conv_tess_prim_to_gs_out(enum tess_primitive_mode prim) +radv_conv_tess_prim_to_gs_out(enum tess_primitive_mode prim) { switch (prim) { case TESS_PRIMITIVE_TRIANGLES: @@ -354,7 +354,7 @@ si_conv_tess_prim_to_gs_out(enum tess_primitive_mode prim) } static uint32_t -si_conv_gl_prim_to_gs_out(unsigned gl_prim) +radv_conv_gl_prim_to_gs_out(unsigned gl_prim) { switch (gl_prim) { case MESA_PRIM_POINTS: @@ -849,7 +849,7 @@ radv_pipeline_init_dynamic_state(const struct radv_device *device, struct radv_g /* Input assembly. */ if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) { - dynamic->vk.ia.primitive_topology = si_translate_prim(state->ia->primitive_topology); + dynamic->vk.ia.primitive_topology = radv_translate_prim(state->ia->primitive_topology); } if (states & RADV_DYNAMIC_PRIMITIVE_RESTART_ENABLE) { @@ -929,7 +929,7 @@ radv_pipeline_init_dynamic_state(const struct radv_device *device, struct radv_g } if (states & RADV_DYNAMIC_POLYGON_MODE) { - dynamic->vk.rs.polygon_mode = si_translate_fill(state->rs->polygon_mode); + dynamic->vk.rs.polygon_mode = radv_translate_fill(state->rs->polygon_mode); } if (states & RADV_DYNAMIC_LINE_STIPPLE_ENABLE) { @@ -1069,7 +1069,7 @@ radv_pipeline_init_dynamic_state(const struct radv_device *device, struct radv_g if (radv_pipeline_has_color_attachments(state->rp)) { if (states & RADV_DYNAMIC_LOGIC_OP) { if ((pipeline->dynamic_states & RADV_DYNAMIC_LOGIC_OP_ENABLE) || state->cb->logic_op_enable) { - dynamic->vk.cb.logic_op = si_translate_blend_logic_op(state->cb->logic_op); + dynamic->vk.cb.logic_op = radv_translate_blend_logic_op(state->cb->logic_op); } } @@ -1879,7 +1879,7 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru } if (state->ia) { - key.vs.topology = si_translate_prim(state->ia->primitive_topology); + key.vs.topology = radv_translate_prim(state->ia->primitive_topology); } if (pipeline->base.type == RADV_PIPELINE_GRAPHICS_LIB && @@ -2381,17 +2381,17 @@ radv_get_rasterization_prim(const struct radv_shader_stage *stages, const struct return -1; if (stages[MESA_SHADER_GEOMETRY].nir) { - rast_prim = si_conv_gl_prim_to_gs_out(stages[MESA_SHADER_GEOMETRY].nir->info.gs.output_primitive); + rast_prim = radv_conv_gl_prim_to_gs_out(stages[MESA_SHADER_GEOMETRY].nir->info.gs.output_primitive); } else if (stages[MESA_SHADER_TESS_EVAL].nir) { if (stages[MESA_SHADER_TESS_EVAL].nir->info.tess.point_mode) { rast_prim = V_028A6C_POINTLIST; } else { - rast_prim = si_conv_tess_prim_to_gs_out(stages[MESA_SHADER_TESS_EVAL].nir->info.tess._primitive_mode); + rast_prim = radv_conv_tess_prim_to_gs_out(stages[MESA_SHADER_TESS_EVAL].nir->info.tess._primitive_mode); } } else if (stages[MESA_SHADER_MESH].nir) { - rast_prim = si_conv_gl_prim_to_gs_out(stages[MESA_SHADER_MESH].nir->info.mesh.primitive_type); + rast_prim = radv_conv_gl_prim_to_gs_out(stages[MESA_SHADER_MESH].nir->info.mesh.primitive_type); } else { - rast_prim = si_conv_prim_to_gs_out(pipeline_key->vs.topology, false); + rast_prim = radv_conv_prim_to_gs_out(pipeline_key->vs.topology, false); } return rast_prim; @@ -3768,17 +3768,18 @@ radv_pipeline_init_vgt_gs_out(struct radv_graphics_pipeline *pipeline, const str uint32_t gs_out; if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) { - gs_out = si_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim); + gs_out = radv_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim); } else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) { if (pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) { gs_out = V_028A6C_POINTLIST; } else { - gs_out = si_conv_tess_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes._primitive_mode); + gs_out = + radv_conv_tess_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes._primitive_mode); } } else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH)) { - gs_out = si_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.output_prim); + gs_out = radv_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.output_prim); } else { - gs_out = si_conv_prim_to_gs_out(si_translate_prim(state->ia->primitive_topology), false); + gs_out = radv_conv_prim_to_gs_out(radv_translate_prim(state->ia->primitive_topology), false); } return gs_out; @@ -3807,7 +3808,7 @@ radv_pipeline_init_extra(struct radv_graphics_pipeline *pipeline, dynamic->vk.ia.primitive_topology = V_008958_DI_PT_RECTLIST; *vgt_gs_out_prim_type = - si_conv_prim_to_gs_out(dynamic->vk.ia.primitive_topology, radv_pipeline_has_ngg(pipeline)); + radv_conv_prim_to_gs_out(dynamic->vk.ia.primitive_topology, radv_pipeline_has_ngg(pipeline)); pipeline->rast_prim = *vgt_gs_out_prim_type; } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 710d03eb8f9..02c5b8bfe40 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1763,15 +1763,15 @@ bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer); void radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer); -void si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs); -void si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs); +void radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs); +void radv_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs); void radv_create_gfx_config(struct radv_device *device); -void si_write_scissors(struct radeon_cmdbuf *cs, int count, const VkRect2D *scissors, const VkViewport *viewports); +void radv_write_scissors(struct radeon_cmdbuf *cs, int count, const VkRect2D *scissors, const VkViewport *viewports); -void si_write_guardband(struct radeon_cmdbuf *cs, int count, const VkViewport *viewports, unsigned rast_prim, - unsigned polygon_mode, float line_width); +void radv_write_guardband(struct radeon_cmdbuf *cs, int count, const VkViewport *viewports, unsigned rast_prim, + unsigned polygon_mode, float line_width); VkResult radv_create_shadow_regs_preamble(const struct radv_device *device, struct radv_queue_state *queue_state); void radv_destroy_shadow_regs_preamble(struct radv_queue_state *queue_state, struct radeon_winsys *ws); @@ -1779,12 +1779,13 @@ void radv_emit_shadow_regs_preamble(struct radeon_cmdbuf *cs, const struct radv_ struct radv_queue_state *queue_state); VkResult radv_init_shadowed_regs_buffer_state(const struct radv_device *device, struct radv_queue *queue); -uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw, bool indirect_draw, - bool count_from_stream_output, uint32_t draw_vertex_count, unsigned topology, - bool prim_restart_enable, unsigned patch_control_points, unsigned num_tess_patches); -void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, enum radv_queue_family qf, - unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, - uint32_t new_fence, uint64_t gfx9_eop_bug_va); +uint32_t radv_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw, bool indirect_draw, + bool count_from_stream_output, uint32_t draw_vertex_count, unsigned topology, + bool prim_restart_enable, unsigned patch_control_points, + unsigned num_tess_patches); +void radv_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, enum radv_queue_family qf, + unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, + uint64_t va, uint32_t new_fence, uint64_t gfx9_eop_bug_va); struct radv_vgt_shader_key { uint8_t tess : 1; @@ -1799,19 +1800,19 @@ struct radv_vgt_shader_key { uint8_t vs_wave32 : 1; }; -void si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, - uint32_t *flush_cnt, uint64_t flush_va, enum radv_queue_family qf, - enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, - uint64_t gfx9_eop_bug_va); -void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer); -void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_visible, unsigned pred_op, - uint64_t va); -void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint64_t dest_va, uint64_t size); -void si_cs_cp_dma_prefetch(const struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va, unsigned size, - bool predicating); -void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va, unsigned size); -void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t size, unsigned value); -void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer); +void radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, + uint32_t *flush_cnt, uint64_t flush_va, enum radv_queue_family qf, + enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, + uint64_t gfx9_eop_bug_va); +void radv_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer); +void radv_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_visible, unsigned pred_op, + uint64_t va); +void radv_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint64_t dest_va, uint64_t size); +void radv_cs_cp_dma_prefetch(const struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va, unsigned size, + bool predicating); +void radv_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va, unsigned size); +void radv_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t size, unsigned value); +void radv_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer); uint32_t radv_get_vgt_index_size(uint32_t type); @@ -1861,11 +1862,11 @@ void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, const str void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, const struct radv_image_view *iview, int cb_idx, uint32_t color_values[2]); -void si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *image, - const struct legacy_surf_level *base_level_info, unsigned plane_id, - unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil, - bool is_storage_image, bool disable_compression, bool enable_write_compression, - uint32_t *state, const struct ac_surf_nbc_view *nbc_view); +void radv_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *image, + const struct legacy_surf_level *base_level_info, unsigned plane_id, + unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil, + bool is_storage_image, bool disable_compression, bool enable_write_compression, + uint32_t *state, const struct ac_surf_nbc_view *nbc_view); void radv_make_texture_descriptor(struct radv_device *device, struct radv_image *image, bool is_storage_image, VkImageViewType view_type, VkFormat vk_format, const VkComponentMapping *mapping, @@ -2629,7 +2630,7 @@ unsigned radv_image_queue_family_mask(const struct radv_image *image, enum radv_ bool radv_image_is_renderable(const struct radv_device *device, const struct radv_image *image); -unsigned si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil); +unsigned radv_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil); struct radeon_bo_metadata; void radv_init_metadata(struct radv_device *device, struct radv_image *image, struct radeon_bo_metadata *metadata); @@ -3020,7 +3021,7 @@ void radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedComma bool radv_dgc_can_preprocess(const struct radv_indirect_command_layout *layout, struct radv_pipeline *pipeline); static inline uint32_t -si_conv_prim_to_gs_out(uint32_t topology, bool is_ngg) +radv_conv_prim_to_gs_out(uint32_t topology, bool is_ngg) { switch (topology) { case V_008958_DI_PT_POINTLIST: @@ -3046,7 +3047,7 @@ si_conv_prim_to_gs_out(uint32_t topology, bool is_ngg) } static inline uint32_t -si_translate_prim(unsigned topology) +radv_translate_prim(unsigned topology) { switch (topology) { case VK_PRIMITIVE_TOPOLOGY_POINT_LIST: @@ -3145,12 +3146,12 @@ radv_get_num_vertices_per_prim(const struct radv_pipeline_key *pipeline_key) return 3; } else { /* Need to add 1, because: V_028A6C_POINTLIST=0, V_028A6C_LINESTRIP=1, V_028A6C_TRISTRIP=2, etc. */ - return si_conv_prim_to_gs_out(pipeline_key->vs.topology, false) + 1; + return radv_conv_prim_to_gs_out(pipeline_key->vs.topology, false) + 1; } } static inline uint32_t -si_translate_fill(VkPolygonMode func) +radv_translate_fill(VkPolygonMode func) { switch (func) { case VK_POLYGON_MODE_FILL: @@ -3166,7 +3167,7 @@ si_translate_fill(VkPolygonMode func) } static inline uint32_t -si_translate_stencil_op(enum VkStencilOp op) +radv_translate_stencil_op(enum VkStencilOp op) { switch (op) { case VK_STENCIL_OP_KEEP: @@ -3191,7 +3192,7 @@ si_translate_stencil_op(enum VkStencilOp op) } static inline uint32_t -si_translate_blend_logic_op(VkLogicOp op) +radv_translate_blend_logic_op(VkLogicOp op) { switch (op) { case VK_LOGIC_OP_CLEAR: @@ -3232,7 +3233,7 @@ si_translate_blend_logic_op(VkLogicOp op) } static inline uint32_t -si_translate_blend_function(VkBlendOp op) +radv_translate_blend_function(VkBlendOp op) { switch (op) { case VK_BLEND_OP_ADD: @@ -3251,7 +3252,7 @@ si_translate_blend_function(VkBlendOp op) } static inline uint32_t -si_translate_blend_factor(enum amd_gfx_level gfx_level, VkBlendFactor factor) +radv_translate_blend_factor(enum amd_gfx_level gfx_level, VkBlendFactor factor) { switch (factor) { case VK_BLEND_FACTOR_ZERO: @@ -3300,7 +3301,7 @@ si_translate_blend_factor(enum amd_gfx_level gfx_level, VkBlendFactor factor) } static inline uint32_t -si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha) +radv_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha) { switch (factor) { case VK_BLEND_FACTOR_ZERO: @@ -3323,7 +3324,7 @@ si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha) } static inline uint32_t -si_translate_blend_opt_function(VkBlendOp op) +radv_translate_blend_opt_function(VkBlendOp op) { switch (op) { case VK_BLEND_OP_ADD: @@ -3342,7 +3343,7 @@ si_translate_blend_opt_function(VkBlendOp op) } static inline bool -si_blend_factor_uses_dst(VkBlendFactor factor) +radv_blend_factor_uses_dst(VkBlendFactor factor) { return factor == VK_BLEND_FACTOR_DST_COLOR || factor == VK_BLEND_FACTOR_DST_ALPHA || factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA || @@ -3391,8 +3392,8 @@ radv_normalize_blend_factor(VkBlendOp op, VkBlendFactor *src_factor, VkBlendFact } } -void si_blend_remove_dst(VkBlendOp *func, VkBlendFactor *src_factor, VkBlendFactor *dst_factor, - VkBlendFactor expected_dst, VkBlendFactor replacement_src); +void radv_blend_remove_dst(VkBlendOp *func, VkBlendFactor *src_factor, VkBlendFactor *dst_factor, + VkBlendFactor expected_dst, VkBlendFactor replacement_src); ALWAYS_INLINE static bool radv_is_streamout_enabled(struct radv_cmd_buffer *cmd_buffer) diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index fc325a2c43c..17da2892d3d 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1625,7 +1625,7 @@ emit_query_flush(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo * path. Small pools don't need any cache flushes * because we use a CP dma clear. */ - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); } } } @@ -1935,7 +1935,7 @@ gfx10_copy_gds_query_gfx(struct radv_cmd_buffer *cmd_buffer, uint32_t gds_offset { /* Make sure GDS is idle before copying the value. */ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_L2; - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); gfx10_copy_gds_query(cmd_buffer->cs, gds_offset, va); } @@ -2269,9 +2269,9 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY; } - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, - V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, avail_va, 1, - cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, + V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, avail_va, + 1, cmd_buffer->gfx9_eop_bug_va); break; } case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT: @@ -2432,9 +2432,9 @@ radv_write_timestamp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, VkPipeline radeon_emit(cs, va); radeon_emit(cs, va >> 32); } else { - si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, - V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_TIMESTAMP, va, 0, - cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, cmd_buffer->qf, + V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_TIMESTAMP, va, 0, + cmd_buffer->gfx9_eop_bug_va); } } @@ -2471,7 +2471,7 @@ radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 sta cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH; } - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_queries); @@ -2502,7 +2502,7 @@ radv_CmdWriteAccelerationStructuresPropertiesKHR(VkCommandBuffer commandBuffer, radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo); - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 6 * accelerationStructureCount); diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 294e49b1013..92494088606 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -805,14 +805,14 @@ radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_device *device) radv_cs_add_buffer(device->ws, cs, device->gfx_init); } else { - si_emit_graphics(device, cs); + radv_emit_graphics(device, cs); } } static void radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_device *device) { - si_emit_compute(device, cs); + radv_emit_compute(device, cs); } static VkResult @@ -1061,7 +1061,7 @@ radv_update_preamble_cs(struct radv_queue_state *queue, struct radv_device *devi flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH; } - si_cs_emit_cache_flush(ws, cs, gfx_level, NULL, 0, queue->qf, flush_bits, &sqtt_flush_bits, 0); + radv_cs_emit_cache_flush(ws, cs, gfx_level, NULL, 0, queue->qf, flush_bits, &sqtt_flush_bits, 0); } result = ws->cs_finalize(cs); @@ -1301,9 +1301,9 @@ radv_create_gang_wait_preambles_postambles(struct radv_queue *queue) */ radv_cp_wait_mem(leader_post_cs, queue->state.qf, WAIT_REG_MEM_GREATER_OR_EQUAL, leader_wait_va, 1, 0xffffffff); radv_cs_write_data(device, leader_post_cs, queue->state.qf, V_370_ME, leader_wait_va, 1, &zero, false); - si_cs_emit_write_event_eop(ace_post_cs, device->physical_device->rad_info.gfx_level, RADV_QUEUE_COMPUTE, - V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, leader_wait_va, - 1, 0); + radv_cs_emit_write_event_eop(ace_post_cs, device->physical_device->rad_info.gfx_level, RADV_QUEUE_COMPUTE, + V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, + leader_wait_va, 1, 0); r = ws->cs_finalize(leader_pre_cs); if (r != VK_SUCCESS) diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index cafdf607a70..20151460c11 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -88,7 +88,7 @@ radv_emit_wait_for_idle(const struct radv_device *device, struct radeon_cmdbuf * { const enum radv_queue_family qf = radv_ip_to_queue_family(family); enum rgp_flush_bits sqtt_flush_bits = 0; - si_cs_emit_cache_flush( + radv_cs_emit_cache_flush( device->ws, cs, device->physical_device->rad_info.gfx_level, NULL, 0, qf, (family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) | diff --git a/src/amd/vulkan/radv_video.c b/src/amd/vulkan/radv_video.c index 38feb1b553d..7591d4e6143 100644 --- a/src/amd/vulkan/radv_video.c +++ b/src/amd/vulkan/radv_video.c @@ -114,7 +114,7 @@ radv_vcn_sq_tail(struct radeon_cmdbuf *cs, struct rvcn_sq_var *sq) /* generate an stream handle */ static unsigned -si_vid_alloc_stream_handle(struct radv_physical_device *pdevice) +radv_vid_alloc_stream_handle(struct radv_physical_device *pdevice) { unsigned stream_handle = pdevice->stream_handle_base; @@ -313,7 +313,7 @@ radv_CreateVideoSessionKHR(VkDevice _device, const VkVideoSessionCreateInfoKHR * return VK_ERROR_FEATURE_NOT_PRESENT; } - vid->stream_handle = si_vid_alloc_stream_handle(device->physical_device); + vid->stream_handle = radv_vid_alloc_stream_handle(device->physical_device); vid->dbg_frame_cnt = 0; vid->db_alignment = radv_video_get_db_alignment( device->physical_device, vid->vk.max_coded.width, diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index caea3e1a10d..89666039d32 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -33,8 +33,8 @@ #include "sid.h" static void -si_write_harvested_raster_configs(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs, - unsigned raster_config, unsigned raster_config_1) +radv_write_harvested_raster_configs(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs, + unsigned raster_config, unsigned raster_config_1) { unsigned num_se = MAX2(physical_device->rad_info.max_se, 1); unsigned raster_config_se[4]; @@ -70,7 +70,7 @@ si_write_harvested_raster_configs(struct radv_physical_device *physical_device, } void -si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) +radv_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) { const struct radeon_info *info = &device->physical_device->rad_info; @@ -170,7 +170,7 @@ radv_pack_float_12p4(float x) } static void -si_set_raster_config(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs) +radv_set_raster_config(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs) { unsigned num_rb = MIN2(physical_device->rad_info.max_render_backends, 16); uint64_t rb_mask = physical_device->rad_info.enabled_rb_mask; @@ -186,12 +186,12 @@ si_set_raster_config(struct radv_physical_device *physical_device, struct radeon if (physical_device->rad_info.gfx_level >= GFX7) radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } else { - si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1); + radv_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1); } } void -si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) +radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) { struct radv_physical_device *physical_device = device->physical_device; @@ -210,7 +210,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) } if (physical_device->rad_info.gfx_level <= GFX8) - si_set_raster_config(physical_device, cs); + radv_set_raster_config(physical_device, cs); /* Emulated in shader code on GFX9+. */ if (physical_device->rad_info.gfx_level >= GFX9) @@ -627,7 +627,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_set_uconfig_reg(cs, R_03092C_GE_MULTI_PRIM_IB_RESET_EN, S_03092C_DISABLE_FOR_AUTO_INDEX(1)); } - si_emit_compute(device, cs); + radv_emit_compute(device, cs); } void @@ -639,7 +639,7 @@ radv_create_gfx_config(struct radv_device *device) radeon_check_space(device->ws, cs, 512); - si_emit_graphics(device, cs); + radv_emit_graphics(device, cs); while (cs->cdw & 7) { if (device->physical_device->rad_info.gfx_ib_pad_with_type2) @@ -689,7 +689,7 @@ radv_get_viewport_xform(const VkViewport *viewport, float scale[3], float transl } static VkRect2D -si_scissor_from_viewport(const VkViewport *viewport) +radv_scissor_from_viewport(const VkViewport *viewport) { float scale[3], translate[3]; VkRect2D rect; @@ -705,7 +705,7 @@ si_scissor_from_viewport(const VkViewport *viewport) } static VkRect2D -si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) +radv_intersect_scissor(const VkRect2D *a, const VkRect2D *b) { VkRect2D ret; ret.offset.x = MAX2(a->offset.x, b->offset.x); @@ -716,7 +716,7 @@ si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) } void -si_write_scissors(struct radeon_cmdbuf *cs, int count, const VkRect2D *scissors, const VkViewport *viewports) +radv_write_scissors(struct radeon_cmdbuf *cs, int count, const VkRect2D *scissors, const VkViewport *viewports) { int i; @@ -725,8 +725,8 @@ si_write_scissors(struct radeon_cmdbuf *cs, int count, const VkRect2D *scissors, radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, count * 2); for (i = 0; i < count; i++) { - VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i); - VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor); + VkRect2D viewport_scissor = radv_scissor_from_viewport(viewports + i); + VkRect2D scissor = radv_intersect_scissor(&scissors[i], &viewport_scissor); radeon_emit( cs, S_028250_TL_X(scissor.offset.x) | S_028250_TL_Y(scissor.offset.y) | S_028250_WINDOW_OFFSET_DISABLE(1)); @@ -736,8 +736,8 @@ si_write_scissors(struct radeon_cmdbuf *cs, int count, const VkRect2D *scissors, } void -si_write_guardband(struct radeon_cmdbuf *cs, int count, const VkViewport *viewports, unsigned rast_prim, - unsigned polygon_mode, float line_width) +radv_write_guardband(struct radeon_cmdbuf *cs, int count, const VkViewport *viewports, unsigned rast_prim, + unsigned polygon_mode, float line_width) { const bool draw_points = radv_rast_prim_is_point(rast_prim) || radv_polygon_mode_is_point(polygon_mode); const bool draw_lines = radv_rast_prim_is_line(rast_prim) || radv_polygon_mode_is_line(polygon_mode); @@ -816,9 +816,9 @@ static const struct radv_prim_vertex_count prim_size_table[] = { }; uint32_t -si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw, bool indirect_draw, - bool count_from_stream_output, uint32_t draw_vertex_count, unsigned topology, - bool prim_restart_enable, unsigned patch_control_points, unsigned num_tess_patches) +radv_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw, bool indirect_draw, + bool count_from_stream_output, uint32_t draw_vertex_count, unsigned topology, + bool prim_restart_enable, unsigned patch_control_points, unsigned num_tess_patches) { const struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info; const unsigned max_primgroup_in_wave = 2; @@ -949,9 +949,9 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dra } void -si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, enum radv_queue_family qf, - unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, - uint32_t new_fence, uint64_t gfx9_eop_bug_va) +radv_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, enum radv_queue_family qf, + unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, + uint32_t new_fence, uint64_t gfx9_eop_bug_va) { if (qf == RADV_QUEUE_TRANSFER) { radeon_emit(cs, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, SDMA_FENCE_MTYPE_UC)); @@ -1042,7 +1042,7 @@ si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_leve } static void -si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl) +radv_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl) { if (is_mec || is_gfx9) { uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff; @@ -1238,11 +1238,11 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level assert(flush_cnt); (*flush_cnt)++; - si_cs_emit_write_event_eop(cs, gfx_level, qf, cb_db_event, - S_490_GLM_WB(glm_wb) | S_490_GLM_INV(glm_inv) | S_490_GLV_INV(glv_inv) | - S_490_GL1_INV(gl1_inv) | S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) | - S_490_SEQ(gcr_seq), - EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, gfx_level, qf, cb_db_event, + S_490_GLM_WB(glm_wb) | S_490_GLM_INV(glm_inv) | S_490_GLV_INV(glv_inv) | + S_490_GL1_INV(gl1_inv) | S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) | + S_490_SEQ(gcr_seq), + EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va); radv_cp_wait_mem(cs, qf, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); } @@ -1296,10 +1296,10 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level } void -si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, - uint32_t *flush_cnt, uint64_t flush_va, enum radv_queue_family qf, - enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, - uint64_t gfx9_eop_bug_va) +radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, + uint32_t *flush_cnt, uint64_t flush_va, enum radv_queue_family qf, + enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, + uint64_t gfx9_eop_bug_va) { unsigned cp_coher_cntl = 0; uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB); @@ -1332,8 +1332,8 @@ si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum /* Necessary for DCC */ if (gfx_level >= GFX8) { - si_cs_emit_write_event_eop(cs, gfx_level, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM, - EOP_DATA_SEL_DISCARD, 0, 0, gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, gfx_level, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM, + EOP_DATA_SEL_DISCARD, 0, 0, gfx9_eop_bug_va); } *sqtt_flush_bits |= RGP_FLUSH_FLUSH_CB | RGP_FLUSH_INVAL_CB; @@ -1414,8 +1414,8 @@ si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum assert(flush_cnt); (*flush_cnt)++; - si_cs_emit_write_event_eop(cs, gfx_level, false, cb_db_event, tc_flags, EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, - flush_va, *flush_cnt, gfx9_eop_bug_va); + radv_cs_emit_write_event_eop(cs, gfx_level, false, cb_db_event, tc_flags, EOP_DST_SEL_MEM, + EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va); radv_cp_wait_mem(cs, qf, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); } @@ -1444,9 +1444,9 @@ si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum } if ((flush_bits & RADV_CMD_FLAG_INV_L2) || (gfx_level <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) { - si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, - cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) | - S_0301F0_TC_WB_ACTION_ENA(gfx_level >= GFX8)); + radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, + cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) | + S_0301F0_TC_WB_ACTION_ENA(gfx_level >= GFX8)); cp_coher_cntl = 0; *sqtt_flush_bits |= RGP_FLUSH_INVAL_L2 | RGP_FLUSH_INVAL_VMEM_L0; @@ -1458,14 +1458,14 @@ si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum * * WB doesn't work without NC. */ - si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, - cp_coher_cntl | S_0301F0_TC_WB_ACTION_ENA(1) | S_0301F0_TC_NC_ACTION_ENA(1)); + radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, + cp_coher_cntl | S_0301F0_TC_WB_ACTION_ENA(1) | S_0301F0_TC_NC_ACTION_ENA(1)); cp_coher_cntl = 0; *sqtt_flush_bits |= RGP_FLUSH_FLUSH_L2 | RGP_FLUSH_INVAL_VMEM_L0; } if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) { - si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1)); + radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1)); cp_coher_cntl = 0; *sqtt_flush_bits |= RGP_FLUSH_INVAL_VMEM_L0; @@ -1476,7 +1476,7 @@ si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum * Therefore, it should be last. Done in PFP. */ if (cp_coher_cntl) - si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl); + radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl); if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) { if (qf == RADV_QUEUE_GENERAL) { @@ -1496,7 +1496,7 @@ si_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum } void -si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) +radv_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) { bool is_compute = cmd_buffer->qf == RADV_QUEUE_COMPUTE; @@ -1512,10 +1512,10 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) return; } - si_cs_emit_cache_flush(cmd_buffer->device->ws, cmd_buffer->cs, - cmd_buffer->device->physical_device->rad_info.gfx_level, &cmd_buffer->gfx9_fence_idx, - cmd_buffer->gfx9_fence_va, radv_cmd_buffer_uses_mec(cmd_buffer), cmd_buffer->state.flush_bits, - &cmd_buffer->state.sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va); + radv_cs_emit_cache_flush( + cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.gfx_level, + &cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va, radv_cmd_buffer_uses_mec(cmd_buffer), + cmd_buffer->state.flush_bits, &cmd_buffer->state.sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va); if (unlikely(cmd_buffer->device->trace_bo)) radv_cmd_buffer_trace_emit(cmd_buffer); @@ -1540,7 +1540,7 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) /* sets the CP predication state using a boolean stored at va */ void -si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_visible, unsigned pred_op, uint64_t va) +radv_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_visible, unsigned pred_op, uint64_t va) { uint32_t op = 0; @@ -1600,8 +1600,8 @@ cp_dma_max_byte_count(enum amd_gfx_level gfx_level) * clear value. */ static void -si_cs_emit_cp_dma(struct radv_device *device, struct radeon_cmdbuf *cs, bool predicating, uint64_t dst_va, - uint64_t src_va, unsigned size, unsigned flags) +radv_cs_emit_cp_dma(struct radv_device *device, struct radeon_cmdbuf *cs, bool predicating, uint64_t dst_va, + uint64_t src_va, unsigned size, unsigned flags) { uint32_t header = 0, command = 0; @@ -1658,13 +1658,13 @@ si_cs_emit_cp_dma(struct radv_device *device, struct radeon_cmdbuf *cs, bool pre } static void -si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src_va, unsigned size, unsigned flags) +radv_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src_va, unsigned size, unsigned flags) { struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_device *device = cmd_buffer->device; bool predicating = cmd_buffer->state.predicating; - si_cs_emit_cp_dma(device, cs, predicating, dst_va, src_va, size, flags); + radv_cs_emit_cp_dma(device, cs, predicating, dst_va, src_va, size, flags); /* CP DMA is executed in ME, but index buffers are read by PFP. * This ensures that ME (CP DMA) is idle before PFP starts fetching @@ -1686,8 +1686,8 @@ si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src } void -si_cs_cp_dma_prefetch(const struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va, unsigned size, - bool predicating) +radv_cs_cp_dma_prefetch(const struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va, unsigned size, + bool predicating) { struct radeon_winsys *ws = device->ws; enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; @@ -1723,23 +1723,23 @@ si_cs_cp_dma_prefetch(const struct radv_device *device, struct radeon_cmdbuf *cs } void -si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va, unsigned size) +radv_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va, unsigned size) { - si_cs_cp_dma_prefetch(cmd_buffer->device, cmd_buffer->cs, va, size, cmd_buffer->state.predicating); + radv_cs_cp_dma_prefetch(cmd_buffer->device, cmd_buffer->cs, va, size, cmd_buffer->state.predicating); if (unlikely(cmd_buffer->device->trace_bo)) radv_cmd_buffer_trace_emit(cmd_buffer); } static void -si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count, uint64_t remaining_size, unsigned *flags) +radv_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count, uint64_t remaining_size, unsigned *flags) { /* Flush the caches for the first copy only. * Also wait for the previous CP DMA operations. */ if (cmd_buffer->state.flush_bits) { - si_emit_cache_flush(cmd_buffer); + radv_emit_cache_flush(cmd_buffer); *flags |= CP_DMA_RAW_WAIT; } @@ -1751,7 +1751,7 @@ si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count, uint6 } static void -si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size) +radv_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size) { uint64_t va; uint32_t offset; @@ -1766,13 +1766,13 @@ si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size) va = radv_buffer_get_va(cmd_buffer->upload.upload_bo); va += offset; - si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags); + radv_cp_dma_prepare(cmd_buffer, size, size, &dma_flags); - si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags); + radv_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags); } void -si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint64_t dest_va, uint64_t size) +radv_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint64_t dest_va, uint64_t size) { enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level; uint64_t main_src_va, main_dest_va; @@ -1823,11 +1823,11 @@ si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint6 dma_flags |= CP_DMA_USE_L2; } - si_cp_dma_prepare(cmd_buffer, byte_count, size + skipped_size + realign_size, &dma_flags); + radv_cp_dma_prepare(cmd_buffer, byte_count, size + skipped_size + realign_size, &dma_flags); dma_flags &= ~CP_DMA_SYNC; - si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va, byte_count, dma_flags); + radv_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va, byte_count, dma_flags); size -= byte_count; main_src_va += byte_count; @@ -1837,16 +1837,16 @@ si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint6 if (skipped_size) { unsigned dma_flags = 0; - si_cp_dma_prepare(cmd_buffer, skipped_size, size + skipped_size + realign_size, &dma_flags); + radv_cp_dma_prepare(cmd_buffer, skipped_size, size + skipped_size + realign_size, &dma_flags); - si_emit_cp_dma(cmd_buffer, dest_va, src_va, skipped_size, dma_flags); + radv_emit_cp_dma(cmd_buffer, dest_va, src_va, skipped_size, dma_flags); } if (realign_size) - si_cp_dma_realign_engine(cmd_buffer, realign_size); + radv_cp_dma_realign_engine(cmd_buffer, realign_size); } void -si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t size, unsigned value) +radv_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t size, unsigned value) { if (!size) return; @@ -1872,10 +1872,10 @@ si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t dma_flags |= CP_DMA_USE_L2; } - si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags); + radv_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags); /* Emit the clear packet. */ - si_emit_cp_dma(cmd_buffer, va, value, byte_count, dma_flags); + radv_emit_cp_dma(cmd_buffer, va, value, byte_count, dma_flags); size -= byte_count; va += byte_count; @@ -1883,7 +1883,7 @@ si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t } void -si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer) +radv_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer) { if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX7) return; @@ -1897,7 +1897,7 @@ si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer) * DMA request, however, the CP will see the sync flag and still wait * for all DMAs to complete. */ - si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC); + radv_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC); cmd_buffer->state.dma_is_busy = false; }