freedreno/fdl: Set LOSSLESSCOMPEN for image when ubwc is enabled on a7xx
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
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95104707f1
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4dc75fc723
7 changed files with 34 additions and 16 deletions
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@ -419,6 +419,7 @@ fdl6_view_init(struct fdl6_view *view, const struct fdl_layout **layouts,
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view->RB_MRT_BUF_INFO =
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A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
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A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(color_format) |
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COND(args->chip >= A7XX && ubwc_enabled, A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN) |
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A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(color_swap);
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view->SP_FS_MRT_REG =
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@ -274,6 +274,7 @@ enum fdl_chroma_location {
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};
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struct fdl_view_args {
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uint32_t chip;
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uint64_t iova;
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uint32_t base_miplevel;
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uint32_t level_count;
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@ -1708,6 +1708,7 @@ tu6_dirty_lrz_fc(struct tu_cmd_buffer *cmd,
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}
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TU_GENX(tu6_dirty_lrz_fc);
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template<chip CHIP>
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static void
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tu_image_view_copy_blit(struct fdl6_view *iview,
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struct tu_image *image,
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@ -1728,6 +1729,7 @@ tu_image_view_copy_blit(struct fdl6_view *iview,
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&image->layout[tu6_plane_index(image->vk.format, aspect_mask)];
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const struct fdl_view_args args = {
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.chip = CHIP,
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.iova = image->iova,
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.base_miplevel = subres->mipLevel,
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.level_count = 1,
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@ -1742,6 +1744,7 @@ tu_image_view_copy_blit(struct fdl6_view *iview,
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fdl6_view_init(iview, &layout, &args, false);
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}
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template<chip CHIP>
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static void
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tu_image_view_copy(struct fdl6_view *iview,
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struct tu_image *image,
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@ -1749,9 +1752,10 @@ tu_image_view_copy(struct fdl6_view *iview,
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const VkImageSubresourceLayers *subres,
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uint32_t layer)
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{
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tu_image_view_copy_blit(iview, image, format, subres, layer, false);
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tu_image_view_copy_blit<CHIP>(iview, image, format, subres, layer, false);
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}
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template<chip CHIP>
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static void
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tu_image_view_blit(struct fdl6_view *iview,
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struct tu_image *image,
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@ -1761,7 +1765,7 @@ tu_image_view_blit(struct fdl6_view *iview,
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enum pipe_format format =
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tu6_plane_format(image->vk.format, tu6_plane_index(image->vk.format,
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subres->aspectMask));
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tu_image_view_copy_blit(iview, image, format, subres, layer, false);
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tu_image_view_copy_blit<CHIP>(iview, image, format, subres, layer, false);
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}
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template <chip CHIP>
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@ -1867,15 +1871,16 @@ tu6_blit_image(struct tu_cmd_buffer *cmd,
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}
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struct fdl6_view dst, src;
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tu_image_view_blit(&dst, dst_image, &info->dstSubresource,
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MIN2(info->dstOffsets[0].z, info->dstOffsets[1].z));
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tu_image_view_blit<CHIP>(
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&dst, dst_image, &info->dstSubresource,
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MIN2(info->dstOffsets[0].z, info->dstOffsets[1].z));
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if (z_scale) {
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tu_image_view_copy_blit(&src, src_image, src_format,
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&info->srcSubresource, 0, true);
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tu_image_view_copy_blit<CHIP>(&src, src_image, src_format,
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&info->srcSubresource, 0, true);
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ops->src(cmd, cs, &src, 0, filter, dst_format);
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} else {
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tu_image_view_blit(&src, src_image, &info->srcSubresource, info->srcOffsets[0].z);
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tu_image_view_blit<CHIP>(&src, src_image, &info->srcSubresource, info->srcOffsets[0].z);
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}
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for (uint32_t i = 0; i < layers; i++) {
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@ -1994,7 +1999,8 @@ tu_copy_buffer_to_image(struct tu_cmd_buffer *cmd,
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(VkSampleCountFlagBits) dst_image->layout[0].nr_samples);
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struct fdl6_view dst;
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tu_image_view_copy(&dst, dst_image, dst_format, &info->imageSubresource, offset.z);
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tu_image_view_copy<CHIP>(&dst, dst_image, dst_format,
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&info->imageSubresource, offset.z);
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for (uint32_t i = 0; i < layers; i++) {
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ops->dst(cs, &dst, i, src_format);
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@ -2077,7 +2083,8 @@ tu_copy_image_to_buffer(struct tu_cmd_buffer *cmd,
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VK_SAMPLE_COUNT_1_BIT);
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struct fdl6_view src;
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tu_image_view_copy(&src, src_image, src_format, &info->imageSubresource, offset.z);
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tu_image_view_copy<CHIP>(&src, src_image, src_format,
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&info->imageSubresource, offset.z);
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for (uint32_t i = 0; i < layers; i++) {
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ops->src(cmd, cs, &src, i, VK_FILTER_NEAREST, dst_format);
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@ -2232,8 +2239,8 @@ tu_copy_image_to_image(struct tu_cmd_buffer *cmd,
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struct fdl6_view dst, src;
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if (use_staging_blit) {
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tu_image_view_copy(&dst, dst_image, dst_format, &info->dstSubresource, dst_offset.z);
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tu_image_view_copy(&src, src_image, src_format, &info->srcSubresource, src_offset.z);
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tu_image_view_copy<CHIP>(&dst, dst_image, dst_format, &info->dstSubresource, dst_offset.z);
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tu_image_view_copy<CHIP>(&src, src_image, src_format, &info->srcSubresource, src_offset.z);
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struct fdl_layout staging_layout = { 0 };
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VkOffset3D staging_offset = { 0 };
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@ -2264,6 +2271,7 @@ tu_copy_image_to_image(struct tu_cmd_buffer *cmd,
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struct fdl6_view staging;
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const struct fdl_layout *staging_layout_ptr = &staging_layout;
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const struct fdl_view_args copy_to_args = {
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.chip = CHIP,
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.iova = staging_bo->iova,
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.base_miplevel = 0,
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.level_count = info->srcSubresource.layerCount,
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@ -2293,6 +2301,7 @@ tu_copy_image_to_image(struct tu_cmd_buffer *cmd,
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tu_cs_emit_wfi(cs);
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const struct fdl_view_args copy_from_args = {
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.chip = CHIP,
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.iova = staging_bo->iova,
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.base_miplevel = 0,
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.level_count = info->srcSubresource.layerCount,
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@ -2315,8 +2324,8 @@ tu_copy_image_to_image(struct tu_cmd_buffer *cmd,
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ops->run(cmd, cs);
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}
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} else {
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tu_image_view_copy(&dst, dst_image, format, &info->dstSubresource, dst_offset.z);
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tu_image_view_copy(&src, src_image, format, &info->srcSubresource, src_offset.z);
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tu_image_view_copy<CHIP>(&dst, dst_image, format, &info->dstSubresource, dst_offset.z);
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tu_image_view_copy<CHIP>(&src, src_image, format, &info->srcSubresource, src_offset.z);
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ops->setup(cmd, cs, format, format, info->dstSubresource.aspectMask,
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0, false, dst_image->layout[0].ubwc,
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@ -2510,8 +2519,8 @@ tu_CmdResolveImage2KHR(VkCommandBuffer commandBuffer,
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coords(ops, cs, info->dstOffset, info->srcOffset, info->extent);
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struct fdl6_view dst, src;
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tu_image_view_blit(&dst, dst_image, &info->dstSubresource, info->dstOffset.z);
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tu_image_view_blit(&src, src_image, &info->srcSubresource, info->srcOffset.z);
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tu_image_view_blit<CHIP>(&dst, dst_image, &info->dstSubresource, info->dstOffset.z);
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tu_image_view_blit<CHIP>(&src, src_image, &info->srcSubresource, info->srcOffset.z);
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for (uint32_t i = 0; i < layers; i++) {
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ops->src(cmd, cs, &src, i, VK_FILTER_NEAREST, dst_format);
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@ -2667,7 +2676,7 @@ clear_image(struct tu_cmd_buffer *cmd,
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.baseArrayLayer = range->baseArrayLayer,
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.layerCount = 1,
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};
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tu_image_view_copy_blit(&dst, image, format, &subresource, 0, false);
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tu_image_view_copy_blit<CHIP>(&dst, image, format, &subresource, 0, false);
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for (uint32_t i = 0; i < layer_count; i++) {
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ops->dst(cs, &dst, i, format);
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@ -213,6 +213,7 @@ tu_image_view_init(struct tu_device *device,
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iview->swizzle);
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struct fdl_view_args args = {};
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args.chip = device->physical_device->info->chip;
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args.iova = image->iova;
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args.base_array_layer = range->baseArrayLayer;
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args.base_miplevel = range->baseMipLevel;
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@ -421,6 +421,8 @@ patch_fb_read_sysmem(struct fd_batch *batch)
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fdl6_get_ubwc_blockwidth(&rsc->layout, &block_width, &block_height);
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struct fdl_view_args args = {
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.chip = A6XX,
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.iova = fd_bo_get_iova(rsc->bo),
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.base_miplevel = psurf->u.tex.level,
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@ -73,6 +73,8 @@ fd6_image_descriptor(struct fd_context *ctx, const struct pipe_image_view *buf,
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size);
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} else {
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struct fdl_view_args args = {
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.chip = A6XX,
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.iova = rsc_iova(buf->resource, 0),
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.base_miplevel = buf->u.tex.level,
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@ -419,6 +419,8 @@ fd6_sampler_view_update(struct fd_context *ctx,
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fdl6_buffer_view_init(so->descriptor, cso->format, swiz, iova, size);
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} else {
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struct fdl_view_args args = {
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.chip = A6XX,
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/* Using relocs for addresses still */
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.iova = 0,
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