intel/isl: Convert Tile4 texture to linear format
Add memcpy function to convert Tile-4 4KB texture to linear format. Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
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Aditya Swarup
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1 changed files with 255 additions and 0 deletions
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@ -766,6 +766,201 @@ ytiled_to_linear(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
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}
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}
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/**
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* Copy texture data from linear to Tile-4 layout.
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*
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* \copydoc tile_copy_fn
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*/
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static inline void
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tile4_to_linear(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
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uint32_t y0, uint32_t y3,
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char *dst, const char *src,
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int32_t dst_pitch,
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uint32_t swizzle_bit,
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isl_mem_copy_fn mem_copy,
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isl_mem_copy_fn mem_copy_align16)
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{
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/* Tile 4 consist of columns that are 'ytile_span' wide and each 64B tile block
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* consists of 4 row of Y-tile ordered data.
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* Each 512B block within a 4kB tile contains 8 such block.
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*
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* To calculate the tiled offset, we need to identify:
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* Block X and Block Y offset at each 512B block boundary in X and Y direction.
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*
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* Refer to the Tile4 layout diagram in linear_to_tile4() function.
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*
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* The tile is divided in 512B blocks[Blk0..Blk7], themselves made of 2
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* rows of 256B sub-blocks
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*
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* Each sub-block is composed of 4 64B elements[cell(0)-cell(3)].
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*
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* Each 64B cell represents 4 rows of data.[cell(0), cell(1), .., cell(63)]
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*
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*
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* Block X - Adds 256B to offset when we encounter block boundary in
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* X direction.(Ex: Blk 0 --> Blk 1(BlkX_off = 256))
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* Block Y - Adds 512B to offset when we encounter block boundary in
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* Y direction.(Ex: Blk 0 --> Blk 3(BlkY_off = 512))
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*
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* (x / ytile_span) * cacheline_size_B //Byte offset in the X dir of the
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* containing 64B block
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* x % ytile_span //Byte offset in X dir within a 64B block/cacheline
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*
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* (y % 4) * 16 // Byte offset of the Y dir within a 64B block/cacheline
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* (y / 4) * 256// Byte offset of the Y dir within 512B block after 1 row
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* of 64B blocks/cachelines
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*
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* The copy destination offset for each range copied is the sum of
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* Block X offset 'BlkX_off', Block Y offset 'BlkY_off', X offset 'xo'
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* and a Y offset 'yo.'
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*/
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const uint32_t column_width = ytile_span;
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const uint32_t tile4_blkh = 4;
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assert(ytile_span * tile4_blkh == 64);
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const uint32_t cacheline_size_B = 64;
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/* Find intermediate Y offsets that are aligned to a 64B element
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* (4 rows), so that we can do fully 64B memcpys on those.
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*/
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uint32_t y1 = MIN2(y3, ALIGN_UP(y0, 4));
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uint32_t y2 = MAX2(y1, ALIGN_DOWN(y3, 4));
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/* xsb0 and xsb1 are the byte offset within a 256B sub block for x0 and x1 */
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uint32_t xsb0 = (x0 % ytile_span) + (x0 / ytile_span) * cacheline_size_B;
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uint32_t xsb1 = (x1 % ytile_span) + (x1 / ytile_span) * cacheline_size_B;
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uint32_t Blkxsb0_off = ALIGN_DOWN(xsb0, 256);
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uint32_t Blky0_off = (y0 / 8) * 512;
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uint32_t BlkX_off, BlkY_off;
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uint32_t x, yo, Y0, Y2;
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/* Y0 determines the initial byte offset in the Y direction */
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Y0 = (y0 / 4) * 256 + (y0 % 4) * 16;
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/* Y2 determines the byte offset required for reaching y2 if y2 doesn't map
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* exactly to 512B block boundary
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*/
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Y2 = y2 * 4 * column_width;
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dst += (ptrdiff_t)y0 * dst_pitch;
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/* To maximize memcpy speed, we do the copy in 3 parts :
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* - copy the first lines that are not aligned to the 64B cell's height (4 rows)
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* - copy the lines that are aligned to 64B cell's height
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* - copy the remaining lines not making up for a full 64B cell's height
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*/
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if (y0 != y1) {
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for (yo = Y0; yo < Y0 + (y1 - y0) * column_width; yo += column_width) {
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uint32_t xo = xsb1;
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if (x0 != x1)
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mem_copy(dst + x0, src + (Blky0_off + Blkxsb0_off) + (xsb0 + yo), x1 - x0);
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for (x = x1; x < x2; x += ytile_span) {
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BlkX_off = ALIGN_DOWN(xo, 256);
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mem_copy_align16(dst + x, src + (Blky0_off + BlkX_off) + (xo + yo), ytile_span);
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xo += cacheline_size_B;
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}
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if (x3 != x2) {
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BlkX_off = ALIGN_DOWN(xo, 256);
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mem_copy_align16(dst + x2, src + (Blky0_off + BlkX_off) + (xo + yo), x3 - x2);
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}
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dst += dst_pitch;
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}
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}
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for (yo = y1 * 4 * column_width; yo < y2 * 4 * column_width; yo += 16 * column_width) {
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uint32_t xo = xsb1;
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BlkY_off = ALIGN_DOWN(yo, 512);
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if (x0 != x1) {
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mem_copy(dst + x0 + 0 * dst_pitch,
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src + (BlkY_off + Blkxsb0_off) + (xsb0 + yo + 0 * column_width),
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x1 - x0);
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mem_copy(dst + x0 + 1 * dst_pitch,
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src + (BlkY_off + Blkxsb0_off) + (xsb0 + yo + 1 * column_width),
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x1 - x0);
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mem_copy(dst + x0 + 2 * dst_pitch,
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src + (BlkY_off + Blkxsb0_off) + (xsb0 + yo + 2 * column_width),
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x1 - x0);
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mem_copy(dst + x0 + 3 * dst_pitch,
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src + (BlkY_off + Blkxsb0_off) + (xsb0 + yo + 3 * column_width),
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x1 - x0);
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}
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for (x = x1; x < x2; x += ytile_span) {
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BlkX_off = ALIGN_DOWN(xo, 256);
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mem_copy_align16(dst + x + 0 * dst_pitch,
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src + (BlkY_off + BlkX_off) + (xo + yo + 0 * column_width),
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ytile_span);
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mem_copy_align16(dst + x + 1 * dst_pitch,
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src + (BlkY_off + BlkX_off) + (xo + yo + 1 * column_width),
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ytile_span);
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mem_copy_align16(dst + x + 2 * dst_pitch,
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src + (BlkY_off + BlkX_off) + (xo + yo + 2 * column_width),
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ytile_span);
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mem_copy_align16(dst + x + 3 * dst_pitch,
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src + (BlkY_off + BlkX_off) + (xo + yo + 3 * column_width),
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ytile_span);
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xo += cacheline_size_B;
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}
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if (x2 != x3) {
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BlkX_off = ALIGN_DOWN(xo, 256);
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mem_copy(dst + x2 + 0 * dst_pitch,
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src + (BlkY_off + BlkX_off) + (xo + yo + 0 * column_width),
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x3 - x2);
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mem_copy(dst + x2 + 1 * dst_pitch,
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src + (BlkY_off + BlkX_off) + (xo + yo + 1 * column_width),
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x3 - x2);
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mem_copy(dst + x2 + 2 * dst_pitch,
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src + (BlkY_off + BlkX_off) + (xo + yo + 2 * column_width),
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x3 - x2);
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mem_copy(dst + x2 + 3 * dst_pitch,
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src + (BlkY_off + BlkX_off) + (xo + yo + 3 * column_width),
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x3 - x2);
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}
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dst += 4 * dst_pitch;
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}
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if (y2 != y3) {
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for (yo = Y2; yo < Y2 + (y3 - y2) * column_width; yo += column_width) {
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uint32_t xo = xsb1;
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BlkY_off = ALIGN_DOWN(yo, 512);
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if (x0 != x1)
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mem_copy(dst + x0, src + (BlkY_off + Blkxsb0_off) + (xsb0 + yo), x1 - x0);
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for (x = x1; x < x2; x += ytile_span) {
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BlkX_off = ALIGN_DOWN(xo, 256);
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mem_copy_align16(dst + x, src + (BlkY_off + BlkX_off) + (xo + yo), ytile_span);
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xo += cacheline_size_B;
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}
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if (x3 != x2) {
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BlkX_off = ALIGN_DOWN(xo, 256);
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mem_copy_align16(dst + x2, src + (BlkY_off + BlkX_off) + (xo + yo), x3 - x2);
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}
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dst += dst_pitch;
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}
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}
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}
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#if defined(INLINE_SSE41)
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static ALWAYS_INLINE void *
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_memcpy_streaming_load(void *dest, const void *src, size_t count)
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@ -1056,6 +1251,61 @@ ytiled_to_linear_faster(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
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dst, src, dst_pitch, swizzle_bit, mem_copy, mem_copy);
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}
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/**
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* Copy texture data from tile4 layout to linear, faster.
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*
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* Same as \ref tile4_to_linear but faster, because it passes constant
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* parameters for common cases, allowing the compiler to inline code
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* optimized for those cases.
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*
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* \copydoc tile_copy_fn
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*/
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static FLATTEN void
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tile4_to_linear_faster(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
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uint32_t y0, uint32_t y1,
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char *dst, const char *src,
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int32_t dst_pitch,
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uint32_t swizzle_bit,
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isl_memcpy_type copy_type)
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{
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isl_mem_copy_fn mem_copy = choose_copy_function(copy_type);
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assert(swizzle_bit == 0);
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if (x0 == 0 && x3 == ytile_width && y0 == 0 && y1 == ytile_height) {
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if (mem_copy == memcpy)
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return tile4_to_linear(0, 0, ytile_width, ytile_width, 0, ytile_height,
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dst, src, dst_pitch, swizzle_bit, memcpy, memcpy);
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else if (mem_copy == rgba8_copy)
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return tile4_to_linear(0, 0, ytile_width, ytile_width, 0, ytile_height,
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dst, src, dst_pitch, swizzle_bit,
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rgba8_copy, rgba8_copy_aligned_src);
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#if defined(INLINE_SSE41)
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else if (copy_type == ISL_MEMCPY_STREAMING_LOAD)
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return tile4_to_linear(0, 0, ytile_width, ytile_width, 0, ytile_height,
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dst, src, dst_pitch, swizzle_bit,
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memcpy, _memcpy_streaming_load);
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#endif
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else
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unreachable("not reached");
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} else {
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if (mem_copy == memcpy)
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return tile4_to_linear(x0, x1, x2, x3, y0, y1,
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dst, src, dst_pitch, swizzle_bit, memcpy, memcpy);
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else if (mem_copy == rgba8_copy)
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return tile4_to_linear(x0, x1, x2, x3, y0, y1,
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dst, src, dst_pitch, swizzle_bit,
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rgba8_copy, rgba8_copy_aligned_src);
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#if defined(INLINE_SSE41)
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else if (copy_type == ISL_MEMCPY_STREAMING_LOAD)
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return tile4_to_linear(x0, x1, x2, x3, y0, y1,
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dst, src, dst_pitch, swizzle_bit,
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memcpy, _memcpy_streaming_load);
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#endif
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else
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unreachable("not reached");
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}
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}
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/**
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* Copy from linear to tiled texture.
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*
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@ -1189,6 +1439,11 @@ tiled_to_linear(uint32_t xt1, uint32_t xt2,
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th = ytile_height;
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span = ytile_span;
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tile_copy = ytiled_to_linear_faster;
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} else if (tiling == ISL_TILING_4) {
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tw = ytile_width;
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th = ytile_height;
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span = ytile_span;
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tile_copy = tile4_to_linear_faster;
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} else {
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unreachable("unsupported tiling");
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}
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