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i965/gen6: Set up layer constraints properly for depth buffers.

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This ports over Chris Forbes' equivalent fixes in gen7_misc_state.c
from commit 77d55ef481.

No Piglit changes on Sandybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Kenneth Graunke 2015-06-25 09:17:38 -07:00
parent f3a620e2a6
commit 6be024f44d
1 changed files with 5 additions and 1 deletions
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6
src/mesa/drivers/dri/i965/gen6_depth_state.c
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@ -73,7 +73,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
rb = (struct gl_renderbuffer*) irb;
if (rb) {
depth = MAX2(rb->Depth, 1);
depth = MAX2(irb->layer_count, 1);
if (rb->TexImage)
gl_target = rb->TexImage->TexObject->Target;
}
@ -89,6 +89,10 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
surftype = BRW_SURFACE_2D;
depth *= 6;
break;
case GL_TEXTURE_3D:
assert(mt);
depth = MAX2(mt->logical_depth0, 1);
/* fallthrough */
default:
surftype = translate_tex_target(gl_target);
break;