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radv: move all per-device keys from radv_pipeline_key to radv_device_cache_key

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radv_device_cache_key contains everything per-device, while
radv_pipeline_key is more like per-pipeline keys.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26948>
This commit is contained in:
Samuel Pitoiset 2024-01-09 09:56:12 +01:00 • committed by Marge Bot
parent 4d44cea3e0
commit 6f6905fc94
8 changed files with 42 additions and 57 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/amd/vulkan/radv_aco_shader_info.h
View file

@ -41,7 +41,7 @@ static inline void radv_aco_convert_ps_epilog_key(struct aco_ps_epilog_info *aco
static inline void
radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv_shader_info *radv,
const struct radv_shader_args *radv_args, const struct radv_pipeline_key *radv_key,
const struct radv_shader_args *radv_args, const struct radv_device_cache_key *radv_key,
const enum amd_gfx_level gfx_level)
{
ASSIGN_FIELD(wave_size);

13
src/amd/vulkan/radv_device.c
View file

@ -712,15 +712,28 @@ radv_device_init_cache_key(struct radv_device *device)
key->clear_lds = device->instance->drirc.clear_lds;
key->cs_wave32 = device->physical_device->cs_wave_size == 32;
key->disable_aniso_single_level =
device->instance->drirc.disable_aniso_single_level && device->physical_device->rad_info.gfx_level < GFX8;
key->disable_shrink_image_store = device->instance->drirc.disable_shrink_image_store;
key->disable_sinking_load_input_fs = device->instance->drirc.disable_sinking_load_input_fs;
key->disable_trunc_coord = device->disable_trunc_coord;
key->dual_color_blend_by_location = device->instance->drirc.dual_color_blend_by_location;
key->emulate_rt = !!(device->instance->perftest_flags & RADV_PERFTEST_EMULATE_RT);
key->ge_wave32 = device->physical_device->ge_wave_size == 32;
key->image_2d_view_of_3d = device->image_2d_view_of_3d && device->physical_device->rad_info.gfx_level == GFX9;
key->invariant_geom = !!(device->instance->debug_flags & RADV_DEBUG_INVARIANT_GEOM);
key->lower_discard_to_demote = !!(device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE);
key->mesh_shader_queries = device->mesh_shader_queries;
key->no_fmask = !!(device->instance->debug_flags & RADV_DEBUG_NO_FMASK);
key->no_rt = !!(device->instance->debug_flags & RADV_DEBUG_NO_RT);
key->primitives_generated_query = device->primitives_generated_query;
key->ps_wave32 = device->physical_device->ps_wave_size == 32;
key->rt_wave64 = device->physical_device->rt_wave_size == 64;
key->split_fma = !!(device->instance->debug_flags & RADV_DEBUG_SPLIT_FMA);
key->ssbo_non_uniform = device->instance->drirc.ssbo_non_uniform;
key->tex_non_uniform = device->instance->drirc.tex_non_uniform;
key->use_llvm = device->physical_device->use_llvm;
key->use_ngg = device->physical_device->use_ngg;
key->use_ngg_culling = device->physical_device->use_ngg_culling;
_mesa_blake3_compute(key, sizeof(*key), device->cache_hash);

14
src/amd/vulkan/radv_pipeline.c
View file

@ -154,18 +154,6 @@ radv_generate_pipeline_key(const struct radv_device *device, const VkPipelineSha
if (flags & VK_PIPELINE_CREATE_2_DISABLE_OPTIMIZATION_BIT_KHR)
key.optimisations_disabled = 1;
key.disable_aniso_single_level =
device->instance->drirc.disable_aniso_single_level && device->physical_device->rad_info.gfx_level < GFX8;
key.disable_trunc_coord = device->disable_trunc_coord;
key.image_2d_view_of_3d = device->image_2d_view_of_3d && device->physical_device->rad_info.gfx_level == GFX9;
key.tex_non_uniform = device->instance->drirc.tex_non_uniform;
key.ssbo_non_uniform = device->instance->drirc.ssbo_non_uniform;
key.disable_shrink_image_store = device->instance->drirc.disable_shrink_image_store;
for (unsigned i = 0; i < num_stages; ++i) {
const VkPipelineShaderStageCreateInfo *const stage = &stages[i];
const VkPipelineShaderStageRequiredSubgroupSizeCreateInfo *const subgroup_size =
@ -586,7 +574,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_key
nir_move_options sink_opts = nir_move_const_undef | nir_move_copies;
if (!pipeline_key->optimisations_disabled) {
if (stage->stage != MESA_SHADER_FRAGMENT || !pipeline_key->disable_sinking_load_input_fs)
if (stage->stage != MESA_SHADER_FRAGMENT || !device->cache_key.disable_sinking_load_input_fs)
sink_opts |= nir_move_load_input;
NIR_PASS(_, stage->nir, nir_opt_sink, sink_opts);

18
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -1893,28 +1893,14 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru
key.vs.provoking_vtx_last = state->rs->provoking_vertex == VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT;
}
if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
key.ps.lower_discard_to_demote = true;
key.ps.force_vrs_enabled = device->force_vrs_enabled && !radv_is_static_vrs_enabled(pipeline, state);
if (device->instance->debug_flags & RADV_DEBUG_INVARIANT_GEOM)
key.invariant_geom = true;
key.use_ngg = device->physical_device->use_ngg;
if ((radv_is_vrs_enabled(pipeline, state) || key.ps.force_vrs_enabled) &&
(device->physical_device->rad_info.family == CHIP_NAVI21 ||
device->physical_device->rad_info.family == CHIP_NAVI22 ||
device->physical_device->rad_info.family == CHIP_VANGOGH))
key.adjust_frag_coord_z = true;
if (device->instance->drirc.disable_sinking_load_input_fs)
key.disable_sinking_load_input_fs = true;
if (device->primitives_generated_query)
key.primitives_generated_query = true;
if (radv_pipeline_needs_ps_epilog(pipeline, lib_flags))
key.ps.has_epilog = true;
@ -1973,8 +1959,6 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru
}
}
key.mesh_shader_queries = device->mesh_shader_queries;
return key;
}
@ -1982,7 +1966,7 @@ static void
radv_fill_shader_info_ngg(struct radv_device *device, const struct radv_pipeline_key *pipeline_key,
struct radv_shader_stage *stages, VkShaderStageFlagBits active_nir_stages)
{
if (pipeline_key->use_ngg) {
if (device->cache_key.use_ngg) {
if (stages[MESA_SHADER_TESS_CTRL].nir) {
stages[MESA_SHADER_TESS_EVAL].info.is_ngg = true;
} else if (stages[MESA_SHADER_VERTEX].nir) {

12
src/amd/vulkan/radv_private.h
View file

@ -880,15 +880,27 @@ struct radv_sqtt_timestamp {
struct radv_device_cache_key {
uint32_t clear_lds : 1;
uint32_t cs_wave32 : 1;
uint32_t disable_aniso_single_level : 1;
uint32_t disable_shrink_image_store : 1;
uint32_t disable_sinking_load_input_fs : 1;
uint32_t disable_trunc_coord : 1;
uint32_t dual_color_blend_by_location : 1;
uint32_t emulate_rt : 1;
uint32_t ge_wave32 : 1;
uint32_t image_2d_view_of_3d : 1;
uint32_t invariant_geom : 1;
uint32_t lower_discard_to_demote : 1;
uint32_t mesh_shader_queries : 1;
uint32_t no_fmask : 1;
uint32_t no_rt : 1;
uint32_t primitives_generated_query : 1;
uint32_t ps_wave32 : 1;
uint32_t rt_wave64 : 1;
uint32_t split_fma : 1;
uint32_t ssbo_non_uniform : 1;
uint32_t tex_non_uniform : 1;
uint32_t use_llvm : 1;
uint32_t use_ngg : 1;
uint32_t use_ngg_culling : 1;
};

18
src/amd/vulkan/radv_shader.c
View file

@ -472,8 +472,8 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
.func = radv_spirv_nir_debug,
.private_data = &spirv_debug_data,
},
.force_tex_non_uniform = key->tex_non_uniform,
.force_ssbo_non_uniform = key->ssbo_non_uniform,
.force_tex_non_uniform = device->cache_key.tex_non_uniform,
.force_ssbo_non_uniform = device->cache_key.ssbo_non_uniform,
};
nir = spirv_to_nir(spirv, stage->spirv.size / 4, spec_entries, num_spec_entries, stage->stage, stage->entrypoint,
&spirv_options, &device->physical_device->nir_options[stage->stage]);
@ -552,7 +552,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
NIR_PASS(_, nir, nir_lower_vars_to_ssa);
NIR_PASS(_, nir, nir_propagate_invariant, key->invariant_geom);
NIR_PASS(_, nir, nir_propagate_invariant, device->cache_key.invariant_geom);
NIR_PASS(_, nir, nir_lower_clip_cull_distance_arrays);
@ -560,7 +560,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
nir->info.stage == MESA_SHADER_GEOMETRY)
NIR_PASS_V(nir, nir_shader_gather_xfb_info);
NIR_PASS(_, nir, nir_lower_discard_or_demote, key->ps.lower_discard_to_demote);
NIR_PASS(_, nir, nir_lower_discard_or_demote, device->cache_key.lower_discard_to_demote);
nir_lower_doubles_options lower_doubles = nir->options->lower_doubles_options;
@ -2495,7 +2495,7 @@ shader_compile(struct radv_device *device, struct nir_shader *const *shaders, in
struct aco_shader_info ac_info;
struct aco_compiler_options ac_opts;
radv_aco_convert_opts(&ac_opts, options, args);
radv_aco_convert_shader_info(&ac_info, info, args, &options->key, options->info->gfx_level);
radv_aco_convert_shader_info(&ac_info, info, args, &device->cache_key, options->info->gfx_level);
aco_compile_shader(&ac_opts, &ac_info, shader_count, shaders, &args->ac, &radv_aco_build_shader_binary,
(void **)&binary);
}
@ -2639,7 +2639,7 @@ radv_create_rt_prolog(struct radv_device *device)
struct radv_shader_binary *binary = NULL;
struct aco_shader_info ac_info;
struct aco_compiler_options ac_opts;
radv_aco_convert_shader_info(&ac_info, &info, &in_args, &options.key, options.info->gfx_level);
radv_aco_convert_shader_info(&ac_info, &info, &in_args, &device->cache_key, options.info->gfx_level);
radv_aco_convert_opts(&ac_opts, &options, &in_args);
aco_compile_rt_prolog(&ac_opts, &ac_info, &in_args.ac, &out_args.ac, &radv_aco_build_shader_binary,
(void **)&binary);
@ -2703,7 +2703,7 @@ radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_ke
struct aco_shader_info ac_info;
struct aco_vs_prolog_info ac_prolog_info;
struct aco_compiler_options ac_opts;
radv_aco_convert_shader_info(&ac_info, &info, &args, &options.key, options.info->gfx_level);
radv_aco_convert_shader_info(&ac_info, &info, &args, &device->cache_key, options.info->gfx_level);
radv_aco_convert_opts(&ac_opts, &options, &args);
radv_aco_convert_vs_prolog_key(&ac_prolog_info, key, &args);
aco_compile_vs_prolog(&ac_opts, &ac_info, &ac_prolog_info, &args.ac, &radv_aco_build_shader_part, (void **)&binary);
@ -2756,7 +2756,7 @@ radv_create_ps_epilog(struct radv_device *device, const struct radv_ps_epilog_ke
struct aco_shader_info ac_info;
struct aco_ps_epilog_info ac_epilog_info = {0};
struct aco_compiler_options ac_opts;
radv_aco_convert_shader_info(&ac_info, &info, &args, &options.key, options.info->gfx_level);
radv_aco_convert_shader_info(&ac_info, &info, &args, &device->cache_key, options.info->gfx_level);
radv_aco_convert_opts(&ac_opts, &options, &args);
radv_aco_convert_ps_epilog_key(&ac_epilog_info, key, &args);
aco_compile_ps_epilog(&ac_opts, &ac_info, &ac_epilog_info, &args.ac, &radv_aco_build_shader_part, (void **)&binary);
@ -2814,7 +2814,7 @@ radv_create_tcs_epilog(struct radv_device *device, const struct radv_tcs_epilog_
struct aco_shader_info ac_info;
struct aco_tcs_epilog_info ac_epilog_info;
struct aco_compiler_options ac_opts;
radv_aco_convert_shader_info(&ac_info, &info, &args, &options.key, options.info->gfx_level);
radv_aco_convert_shader_info(&ac_info, &info, &args, &device->cache_key, options.info->gfx_level);
radv_aco_convert_opts(&ac_opts, &options, &args);
radv_aco_convert_tcs_epilog_key(&ac_epilog_info, key, &args);
aco_compile_tcs_epilog(&ac_opts, &ac_info, &ac_epilog_info, &args.ac, &radv_aco_build_shader_part, (void **)&binary);

12
src/amd/vulkan/radv_shader.h
View file

@ -116,24 +116,13 @@ struct radv_pipeline_key {
uint32_t has_multiview_view_index : 1;
uint32_t optimisations_disabled : 1;
uint32_t invariant_geom : 1;
uint32_t use_ngg : 1;
uint32_t adjust_frag_coord_z : 1;
uint32_t disable_aniso_single_level : 1;
uint32_t disable_trunc_coord : 1;
uint32_t disable_sinking_load_input_fs : 1;
uint32_t disable_shrink_image_store : 1;
uint32_t image_2d_view_of_3d : 1;
uint32_t primitives_generated_query : 1;
uint32_t dynamic_patch_control_points : 1;
uint32_t dynamic_rasterization_samples : 1;
uint32_t dynamic_provoking_vtx_mode : 1;
uint32_t dynamic_line_rast_mode : 1;
uint32_t tex_non_uniform : 1;
uint32_t ssbo_non_uniform : 1;
uint32_t enable_remove_point_size : 1;
uint32_t unknown_rast_prim : 1;
uint32_t mesh_shader_queries : 1;
uint32_t vertex_robustness1 : 1;
uint32_t mesh_fast_launch_2 : 1;
@ -168,7 +157,6 @@ struct radv_pipeline_key {
uint8_t num_samples;
bool sample_shading_enable;
bool lower_discard_to_demote;
bool force_vrs_enabled;
/* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */

10
src/amd/vulkan/radv_shader_info.c
View file

@ -681,7 +681,7 @@ gather_shader_info_gs(struct radv_device *device, const nir_shader *nir, struct
}
static void
gather_shader_info_mesh(const nir_shader *nir, const struct radv_pipeline_key *pipeline_key,
gather_shader_info_mesh(struct radv_device *device, const nir_shader *nir, const struct radv_pipeline_key *pipeline_key,
struct radv_shader_info *info)
{
struct gfx10_ngg_info *ngg_info = &info->ngg_info;
@ -722,7 +722,7 @@ gather_shader_info_mesh(const nir_shader *nir, const struct radv_pipeline_key *p
ngg_info->prim_amp_factor = nir->info.mesh.max_primitives_out;
ngg_info->vgt_esgs_ring_itemsize = 1;
info->ms.has_query = pipeline_key->mesh_shader_queries;
info->ms.has_query = device->cache_key.mesh_shader_queries;
}
static void
@ -977,7 +977,7 @@ gather_shader_info_task(struct radv_device *device, const nir_shader *nir, const
info->cs.linear_taskmesh_dispatch =
nir->info.mesh.ts_mesh_dispatch_dimensions[1] == 1 && nir->info.mesh.ts_mesh_dispatch_dimensions[2] == 1;
info->cs.has_query = pipeline_key->mesh_shader_queries;
info->cs.has_query = device->cache_key.mesh_shader_queries;
}
static uint32_t
@ -1214,7 +1214,7 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
gather_shader_info_vs(device, nir, pipeline_key, info);
break;
case MESA_SHADER_MESH:
gather_shader_info_mesh(nir, pipeline_key, info);
gather_shader_info_mesh(device, nir, pipeline_key, info);
break;
default:
if (gl_shader_stage_is_rt(nir->info.stage))
@ -1525,7 +1525,7 @@ gfx10_get_ngg_query_info(const struct radv_device *device, struct radv_shader_st
info->gs.has_pipeline_stat_query = device->physical_device->emulate_ngg_gs_query_pipeline_stat && !!gs_stage;
info->has_xfb_query = gs_stage ? !!gs_stage->nir->xfb_info : !!es_stage->nir->xfb_info;
info->has_prim_query = pipeline_key->primitives_generated_query || info->has_xfb_query;
info->has_prim_query = device->cache_key.primitives_generated_query || info->has_xfb_query;
}
static void