NeroReflex/mesa
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

intel/genxml/gfx125: Move L1_CACHE_CONTROL to enum

Browse source 
This will allow us to use it in Xe2 genxml.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
This commit is contained in:
Jordan Justen 2022-08-12 13:30:01 -07:00 • committed by Marge Bot
parent 9e97ce59a8
commit 772ce98a81
1 changed files with 8 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

15
src/intel/genxml/gen125.xml
View file

@ -13,6 +13,13 @@
<exclude name="MEDIA_STATE_FLUSH" />
<exclude name="MEDIA_VFE_STATE" />
</import>
<enum name="L1_CACHE_CONTROL" prefix="L1CC">
<value name="WBP" value="0" />
<value name="UC" value="1" />
<value name="WB" value="2" />
<value name="WT" value="3" />
<value name="WS" value="4" />
</enum>
<enum name="PREF_SLM_ALLOCATION_SIZE">
<value name="SLM_ENCODES_0K" value="8" />
<value name="SLM_ENCODES_16K" value="9" />
@ -347,13 +354,7 @@
<field name="Surface Min LOD" start="164" end="167" type="uint" />
<field name="Mip Tail Start LOD" start="168" end="171" type="uint" />
<field name="Coherency Type" start="174" end="174" type="mbz" />
<field name="L1 Cache Control" start="176" end="178" type="uint" prefix="L1CC">
<value name="WBP" value="0" />
<value name="UC" value="1" />
<value name="WB" value="2" />
<value name="WT" value="3" />
<value name="WS" value="4" />
</field>
<field name="L1 Cache Control" start="176" end="178" type="L1_CACHE_CONTROL" />
<field name="EWA Disable For Cube" start="180" end="180" type="bool" />
<field name="Y Offset" start="181" end="183" type="uint" />
<field name="X Offset" start="185" end="191" type="uint" />