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anv: untyped data port flush required when a pipeline sets the VK_ACCESS_2_SHADER_STORAGE_READ_BIT

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VK_ACCESS_2_SHADER_STORAGE_READ_BIT specifies read access to a
storage buffer, physical storage buffer, storage texel buffer, or
storage image in any shader pipeline stage.

Any storage buffers or images written to must be invalidated and
flushed before the shader can access them.

This fixes the following tests on LNL:
  - dEQP-VK.synchronization2.op.single_queue.barrier.write\*_specialized_access_flag

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27212>
(cherry picked from commit 3e93ccbc1b25d3e24f1672eaf1fbdb998ca94173)
This commit is contained in:
Rohan Garg 2024-01-25 13:55:24 +01:00 • committed by Eric Engestrom
parent 2588d3f4b9
commit 77e4a2a06e
2 changed files with 19 additions and 1 deletions
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2
.pick_status.json
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@ -1554,7 +1554,7 @@
"description": "anv: untyped data port flush required when a pipeline sets the VK_ACCESS_2_SHADER_STORAGE_READ_BIT",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

18
src/intel/vulkan/anv_private.h
View file

@ -3288,6 +3288,24 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_2_SHADER_STORAGE_READ_BIT:
/* VK_ACCESS_2_SHADER_STORAGE_READ_BIT specifies read access to a
* storage buffer, physical storage buffer, storage texel buffer, or
* storage image in any shader pipeline stage.
*
* Any storage buffers or images written to must be invalidated and
* flushed before the shader can access them.
*
* Both HDC & Untyped flushes also do invalidation. This is why we use
* this here on Gfx12+.
*
* Gfx11 and prior don't have HDC. Only Data cache flush is available
* and it only operates on the written cache lines.
*/
if (device->info->ver >= 12) {
pipe_bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
}
break;
default:
break; /* Nothing to do */
}