From 7af4d666a765d1f8f048f67638db317a998a3a1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Thu, 11 Jan 2024 17:51:17 +0200 Subject: [PATCH] iris: replace constant cache invalidate with hdc flush MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This implements Wa_14010840176. Cc: mesa-stable Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Part-of: (cherry picked from commit 231ede4f0ca92b33da8b16e7921af9877379c7d1) --- .pick_status.json | 2 +- src/gallium/drivers/iris/iris_state.c | 17 ++++++++++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index c5e1a5447f6..8da2d3e87d6 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -14,7 +14,7 @@ "description": "iris: replace constant cache invalidate with hdc flush", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index ac911b79fe4..51bf69debef 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -9631,6 +9631,22 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, PIPE_CONTROL_CS_STALL, NULL, 0, 0); } + batch_mark_sync_for_pipe_control(batch, flags); + +#if INTEL_NEEDS_WA_14010840176 + /* "If the intention of “constant cache invalidate” is + * to invalidate the L1 cache (which can cache constants), use “HDC + * pipeline flush” instead of Constant Cache invalidate command." + * + * "If L3 invalidate is needed, the w/a should be to set state invalidate + * in the pipe control command, in addition to the HDC pipeline flush." + */ + if (flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE) { + flags &= ~PIPE_CONTROL_CONST_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_FLUSH_HDC | PIPE_CONTROL_STATE_CACHE_INVALIDATE; + } +#endif + /* Emit --------------------------------------------------------------- */ if (INTEL_DEBUG(DEBUG_PIPE_CONTROL)) { @@ -9666,7 +9682,6 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, imm, reason); } - batch_mark_sync_for_pipe_control(batch, flags); iris_batch_sync_region_start(batch); const bool trace_pc =