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i965/gen8: Remove gen<8 checks in gen8 code

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Some assertions in gen8_surface_state.c checked for gen < 8.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Chad Versace 2015-10-08 12:21:19 -07:00
parent 8a0c85b258
commit 82b324c24b
1 changed files with 4 additions and 4 deletions
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8
src/mesa/drivers/dri/i965/gen8_surface_state.c
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@ -221,8 +221,8 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
* "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
* 16 must be used."
*/
assert(brw->gen < 9 || mt->halign == 16);
assert(brw->gen < 8 || mt->num_samples > 1 || mt->halign == 16);
if (brw->gen >= 9 || mt->num_samples == 1)
assert(mt->halign == 16);
}
const uint32_t surf_type = translate_tex_target(target);
@ -470,8 +470,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
* "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
* 16 must be used."
*/
assert(brw->gen < 9 || mt->halign == 16);
assert(brw->gen < 8 || mt->num_samples > 1 || mt->halign == 16);
if (brw->gen >= 9 || mt->num_samples == 1)
assert(mt->halign == 16);
}
uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);