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anv: align buffers to a cache line

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9217
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23794>
This commit is contained in:
Lionel Landwerlin 2023-06-22 12:50:43 +03:00 • committed by Marge Bot
parent 9db5da0f38
commit 8509ebb68a
1 changed files with 5 additions and 5 deletions
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10
src/intel/vulkan/anv_device.c
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@ -4353,11 +4353,11 @@ anv_get_buffer_memory_requirements(struct anv_device *device,
*/
uint32_t memory_types = (1ull << device->physical->memory.type_count) - 1;
/* Base alignment requirement of a cache line */
uint32_t alignment = 16;
if (usage & VK_BUFFER_USAGE_UNIFORM_BUFFER_BIT)
alignment = MAX2(alignment, ANV_UBO_ALIGNMENT);
/* The GPU appears to write back to main memory in cachelines. Writes to a
* buffers should not clobber with writes to another buffers so make sure
* those are in different cachelines.
*/
uint32_t alignment = 64;
pMemoryRequirements->memoryRequirements.size = size;
pMemoryRequirements->memoryRequirements.alignment = alignment;