From 89a6b08cbac717657e222fb250ff1d88d2bd7bbe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Wed, 4 Oct 2023 20:18:52 +0200 Subject: [PATCH] radv: disable HTILE/DCC for concurrent images with transfer queue if unsupported. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DCC and HTILE are only supported by SDMA on GFX10+ (unless disabled by a workaround). Signed-off-by: Timur Kristóf Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_image.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 6d7bd584e52..613583353b0 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -651,6 +651,11 @@ radv_get_surface_flags(struct radv_device *device, struct radv_image *image, uns flags |= RADEON_SURF_PRT | RADEON_SURF_NO_FMASK | RADEON_SURF_NO_HTILE | RADEON_SURF_DISABLE_DCC; } + if (image->queue_family_mask & BITFIELD_BIT(RADV_QUEUE_TRANSFER)) { + if (!device->physical_device->rad_info.sdma_supports_compression) + flags |= RADEON_SURF_DISABLE_DCC | RADEON_SURF_NO_HTILE; + } + /* Disable DCC for VRS rate images because the hw can't handle compression. */ if (pCreateInfo->usage & VK_IMAGE_USAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR) flags |= RADEON_SURF_VRS_RATE | RADEON_SURF_DISABLE_DCC;