intel/fs: Adjust destination size for load ubo on Xe2+
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
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1 changed files with 4 additions and 2 deletions
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@ -6266,7 +6266,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
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bld.emit_uniformize(get_nir_src(ntb, load_offset));
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bld.emit_uniformize(get_nir_src(ntb, load_offset));
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}
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}
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const unsigned total_dwords = ALIGN(instr->num_components, REG_SIZE / 4);
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const unsigned total_dwords =
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ALIGN(instr->num_components, REG_SIZE * reg_unit(devinfo) / 4);
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unsigned loaded_dwords = 0;
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unsigned loaded_dwords = 0;
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const fs_reg packed_consts =
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const fs_reg packed_consts =
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@ -6283,7 +6284,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
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const fs_builder &ubld = block <= 8 ? ubld8 : ubld16;
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const fs_builder &ubld = block <= 8 ? ubld8 : ubld16;
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ubld.emit(SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL,
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ubld.emit(SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL,
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retype(byte_offset(packed_consts, loaded_dwords * 4), BRW_REGISTER_TYPE_UD),
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retype(byte_offset(packed_consts, loaded_dwords * 4), BRW_REGISTER_TYPE_UD),
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srcs, SURFACE_LOGICAL_NUM_SRCS)->size_written = align(block_bytes, REG_SIZE);
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srcs, SURFACE_LOGICAL_NUM_SRCS)->size_written =
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align(block_bytes, REG_SIZE * reg_unit(devinfo));
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loaded_dwords += block;
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loaded_dwords += block;
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