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intel/fs: Adjust destination size for load ubo on Xe2+

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Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
This commit is contained in:
Sagar Ghuge 2023-09-25 17:33:18 -07:00 • committed by Marge Bot
parent e0ce94318b
commit a4947f7bd8
1 changed files with 4 additions and 2 deletions
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6
src/intel/compiler/brw_fs_nir.cpp
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@ -6266,7 +6266,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
bld.emit_uniformize(get_nir_src(ntb, load_offset));
}
const unsigned total_dwords = ALIGN(instr->num_components, REG_SIZE / 4);
const unsigned total_dwords =
ALIGN(instr->num_components, REG_SIZE * reg_unit(devinfo) / 4);
unsigned loaded_dwords = 0;
const fs_reg packed_consts =
@ -6283,7 +6284,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
const fs_builder &ubld = block <= 8 ? ubld8 : ubld16;
ubld.emit(SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL,
retype(byte_offset(packed_consts, loaded_dwords * 4), BRW_REGISTER_TYPE_UD),
srcs, SURFACE_LOGICAL_NUM_SRCS)->size_written = align(block_bytes, REG_SIZE);
srcs, SURFACE_LOGICAL_NUM_SRCS)->size_written =
align(block_bytes, REG_SIZE * reg_unit(devinfo));
loaded_dwords += block;