From a4bb6d7c722b9ffa2e911ed4e1cac91384cfcc11 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Fri, 9 Jun 2023 10:10:24 +0300 Subject: [PATCH] anv: remove BDW specific WA for CS stall enable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This note is in BDW specs but not anymore in gfx9+ specs. Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index e6fab0f82c2..7a5af15201f 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1622,29 +1622,6 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, pipe.Address = device->workaround_address; } - /* - * According to the Broadwell documentation, any PIPE_CONTROL with the - * "Command Streamer Stall" bit set must also have another bit set, - * with five different options: - * - * - Render Target Cache Flush - * - Depth Cache Flush - * - Stall at Pixel Scoreboard - * - Post-Sync Operation - * - Depth Stall - * - DC Flush Enable - * - * I chose "Stall at Pixel Scoreboard" since that's what we use in - * mesa and it seems to work fine. The choice is fairly arbitrary. - */ - if (pipe.CommandStreamerStallEnable && - !pipe.RenderTargetCacheFlushEnable && - !pipe.DepthCacheFlushEnable && - !pipe.StallAtPixelScoreboard && - !pipe.PostSyncOperation && - !pipe.DepthStallEnable && - !pipe.DCFlushEnable) - pipe.StallAtPixelScoreboard = true; anv_debug_dump_pc(pipe); }