NeroReflex/mesa
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

freedreno/ir3: Track whether shader needs derivatives

Browse source 
In 1088b788 ("freedreno/ir3: find # of samplers from uniform vars") we
started counting number of samplers based on the uniform vars instead
of number of cat5 instructions.  We used the number of samplers to
determine whether to enable derivatives, but when we only use
derivatives and no samplers, that now breaks.  Track whether we need
derivatives explicitly and use that to enable the state.

Fixes: 1088b788 ("freedreno/ir3: find # of samplers from uniform vars")
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Kristian H. Kristensen 2019-03-25 14:12:41 -07:00
parent 12f11e6fe6
commit a752422bd4
6 changed files with 12 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/freedreno/ir3/ir3.h
View file

@ -1028,7 +1028,7 @@ int ir3_ra(struct ir3 *ir3, gl_shader_stage type,
bool frag_coord, bool frag_face);
/* legalize: */
void ir3_legalize(struct ir3 *ir, bool *has_ssbo, int *max_bary);
void ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_bary);
/* ************************************************************************* */
/* instruction helpers */

2
src/freedreno/ir3/ir3_compiler_nir.c
View file

@ -2798,7 +2798,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
/* We need to do legalize after (for frag shader's) the "bary.f"
* offsets (inloc) have been assigned.
*/
ir3_legalize(ir, &so->has_ssbo, &max_bary);
ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
printf("AFTER LEGALIZE:\n");

5
src/freedreno/ir3/ir3_legalize.c
View file

@ -42,6 +42,7 @@
struct ir3_legalize_ctx {
struct ir3_compiler *compiler;
bool has_ssbo;
bool need_pixlod;
int max_bary;
};
@ -218,6 +219,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
if (is_tex(n)) {
regmask_set(&state->needs_sy, n->regs[0]);
ctx->need_pixlod = true;
} else if (n->opc == OPC_RESINFO) {
regmask_set(&state->needs_ss, n->regs[0]);
ir3_NOP(block)->flags |= IR3_INSTR_SS;
@ -471,7 +473,7 @@ mark_convergence_points(struct ir3 *ir)
}
void
ir3_legalize(struct ir3 *ir, bool *has_ssbo, int *max_bary)
ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_bary)
{
struct ir3_legalize_ctx *ctx = rzalloc(ir, struct ir3_legalize_ctx);
bool progress;
@ -493,6 +495,7 @@ ir3_legalize(struct ir3 *ir, bool *has_ssbo, int *max_bary)
} while (progress);
*has_ssbo = ctx->has_ssbo;
*need_pixlod = ctx->need_pixlod;
*max_bary = ctx->max_bary;
do {

3
src/freedreno/ir3/ir3_shader.h
View file

@ -431,6 +431,9 @@ struct ir3_shader_variant {
/* do we have one or more SSBO instructions: */
bool has_ssbo;
/* do we need derivatives: */
bool need_pixlod;
/* do we have kill, image write, etc (which prevents early-z): */
bool no_earlyz;

2
src/gallium/drivers/freedreno/a6xx/fd6_compute.c
View file

@ -96,7 +96,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
COND(v->num_samp > 0, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE));
COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE));
OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
OUT_RING(ring, 0x41);

4
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View file

@ -396,7 +396,7 @@ setup_stateobj(struct fd_ringbuffer *ring,
A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(s[VS].v->branchstack) |
COND(s[VS].v->num_samp > 0, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
COND(s[VS].v->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
struct ir3_shader_linkage l = {0};
ir3_link_shaders(&l, s[VS].v, s[FS].v);
@ -518,7 +518,7 @@ setup_stateobj(struct fd_ringbuffer *ring,
A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(s[FS].v->branchstack) |
COND(s[FS].v->num_samp > 0, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
COND(s[FS].v->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
OUT_RING(ring, 0); /* XXX */