From ae4628d3d6ce541560afe90da48ebc20d101cbdc Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 3 Jan 2024 15:18:31 +0100 Subject: [PATCH] radv: do not program COMPUTE_MAX_WAVE_ID (GDS register) on GFX6 Ported from RadeonSI c2359797. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/si_cmd_buffer.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 89666039d32..f795f020fd0 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -117,17 +117,7 @@ radv_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0); } - /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID - * and is now per pipe, so it should be handled in the - * kernel if we want to use something other than the default value, - * which is now 0x22f. - */ if (device->physical_device->rad_info.gfx_level <= GFX6) { - /* XXX: This should be: - * (number of compute units) * 4 * (waves per simd) - 1 */ - - radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */); - if (device->border_color_data.bo) { uint64_t bc_va = radv_buffer_get_va(device->border_color_data.bo); radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);