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nir: Mark nir_intrinsic_load_global_block_intel as divergent

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This is divergent because it specifically loads sequential values into
successive SIMD lanes.

No shader-db or fossil-db changes on any Intel platform.

Fixes: 9f44a26462 ("nir/divergence: handle load_global_block_intel")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27044>
(cherry picked from commit 75de4458a1350ac6f3843e4f8da7a69717c92687)
This commit is contained in:
Ian Romanick 2024-01-11 13:14:47 -08:00 • committed by Eric Engestrom
parent e7244292ce
commit b067a61c07
2 changed files with 8 additions and 2 deletions
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2
.pick_status.json
View file

@ -124,7 +124,7 @@
"description": "nir: Mark nir_intrinsic_load_global_block_intel as divergent", "description": "nir: Mark nir_intrinsic_load_global_block_intel as divergent",
"nominated": true, "nominated": true,
"nomination_type": 1, "nomination_type": 1,
"resolution": 0, "resolution": 1,
"main_sha": null, "main_sha": null,
"because_sha": "9f44a264623461c98368185b023d99446676e039", "because_sha": "9f44a264623461c98368185b023d99446676e039",
"notes": null "notes": null

8
src/compiler/nir/nir_divergence_analysis.c
View file

@ -189,7 +189,6 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
case nir_intrinsic_load_resume_shader_address_amd: case nir_intrinsic_load_resume_shader_address_amd:
case nir_intrinsic_load_global_const_block_intel: case nir_intrinsic_load_global_const_block_intel:
case nir_intrinsic_load_reloc_const_intel: case nir_intrinsic_load_reloc_const_intel:
case nir_intrinsic_load_global_block_intel:
case nir_intrinsic_load_btd_global_arg_addr_intel: case nir_intrinsic_load_btd_global_arg_addr_intel:
case nir_intrinsic_load_btd_local_arg_addr_intel: case nir_intrinsic_load_btd_local_arg_addr_intel:
case nir_intrinsic_load_mesh_inline_data_intel: case nir_intrinsic_load_mesh_inline_data_intel:
@ -219,6 +218,13 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
is_divergent = false; is_divergent = false;
break; break;
/* This is divergent because it specifically loads sequential values into
* successive SIMD lanes.
*/
case nir_intrinsic_load_global_block_intel:
is_divergent = true;
break;
case nir_intrinsic_decl_reg: case nir_intrinsic_decl_reg:
is_divergent = nir_intrinsic_divergent(instr); is_divergent = nir_intrinsic_divergent(instr);
break; break;