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intel/compiler: Set flag reg to 0 when disabling predication

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Having the reg set with predication disabled shouldn't cause any problems
during the execution. But when decompiling such instruction the flag won't
be shown in the output, so the recompiling will cause
functionally-identical but binary-different code. Fixing this makes
disasm/asm testing easier.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657>
This commit is contained in:
Sviatoslav Peleshko 2023-10-11 11:04:12 +03:00 • committed by Marge Bot
parent a129e136de
commit b5c0b90402
3 changed files with 14 additions and 0 deletions
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6
src/intel/compiler/brw_eu_emit.c
View file

@ -2457,6 +2457,7 @@ void brw_oword_block_read(struct brw_codegen *p,
brw_push_insn_state(p);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
@ -2766,6 +2767,7 @@ brw_send_indirect_message(struct brw_codegen *p,
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_exec_size(p, BRW_EXECUTE_1);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
/* Load the indirect descriptor to an address register using OR so the
@ -2823,6 +2825,7 @@ brw_send_indirect_split_message(struct brw_codegen *p,
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_exec_size(p, BRW_EXECUTE_1);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
/* Load the indirect descriptor to an address register using OR so the
@ -2857,6 +2860,7 @@ brw_send_indirect_split_message(struct brw_codegen *p,
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_exec_size(p, BRW_EXECUTE_1);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
/* Load the indirect extended descriptor to an address register using OR
@ -2953,6 +2957,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_exec_size(p, BRW_EXECUTE_1);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
/* Mask out invalid bits from the surface index to avoid hangs e.g. when
@ -3570,6 +3575,7 @@ brw_broadcast(struct brw_codegen *p,
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
/* Take into account the component size and horizontal stride. */
assert(src.vstride == src.hstride + src.width);

3
src/intel/compiler/brw_fs_generator.cpp
View file

@ -369,6 +369,7 @@ fs_generator::fire_fb_write(fs_inst *inst,
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_MOV(p, offset(retype(payload, BRW_REGISTER_TYPE_UD), 1),
offset(retype(implied_header, BRW_REGISTER_TYPE_UD), 1));
@ -1681,6 +1682,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_set_default_exec_size(p, BRW_EXECUTE_16);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
brw_MOV(p, brw_acc_reg(8), brw_imm_f(0.0f));
last_insn_offset = p->next_insn_offset;
@ -1701,6 +1703,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_set_default_exec_size(p, BRW_EXECUTE_1);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
brw_SYNC(p, TGL_SYNC_NOP);
last_insn_offset = p->next_insn_offset;

5
src/intel/compiler/brw_vec4_generator.cpp
View file

@ -93,6 +93,7 @@ generate_math2_gfx4(struct brw_codegen *p,
brw_push_insn_state(p);
brw_set_default_saturate(p, false);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
brw_pop_insn_state(p);
@ -1198,7 +1199,9 @@ generate_scratch_write(struct brw_codegen *p,
/* If the instruction is predicated, we'll predicate the send, not
* the header setup.
*/
brw_push_insn_state(p);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
gfx6_resolve_implied_move(p, &header, inst->base_mrf);
@ -1209,6 +1212,8 @@ generate_scratch_write(struct brw_codegen *p,
retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
retype(src, BRW_REGISTER_TYPE_D));
brw_pop_insn_state(p);
uint32_t msg_type;
if (devinfo->ver >= 7)