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radv/rt: change RT main shader to MESA_SHADER_INTERSECTION

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22096>
This commit is contained in:
Daniel Schürmann 2023-05-09 12:06:46 +02:00 • committed by Marge Bot
parent 81e48613b9
commit d506fe3397
3 changed files with 11 additions and 11 deletions
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12
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -6464,7 +6464,7 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer,
} else {
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.rt_prolog->bo);
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
cmd_buffer->state.shaders[MESA_SHADER_RAYGEN]->bo);
cmd_buffer->state.shaders[MESA_SHADER_INTERSECTION]->bo);
}
if (unlikely(cmd_buffer->device->trace_bo))
@ -6719,7 +6719,7 @@ radv_bind_shader(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader,
radv_bind_task_shader(cmd_buffer, shader);
break;
case MESA_SHADER_COMPUTE:
case MESA_SHADER_RAYGEN:
case MESA_SHADER_INTERSECTION:
/* no-op */
break;
default:
@ -6762,8 +6762,8 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
return;
radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
radv_bind_shader(cmd_buffer, rt_pipeline->base.base.shaders[MESA_SHADER_RAYGEN],
MESA_SHADER_RAYGEN);
radv_bind_shader(cmd_buffer, rt_pipeline->base.base.shaders[MESA_SHADER_INTERSECTION],
MESA_SHADER_INTERSECTION);
cmd_buffer->state.rt_prolog = rt_pipeline->base.base.shaders[MESA_SHADER_COMPUTE];
cmd_buffer->state.rt_pipeline = rt_pipeline;
@ -10132,9 +10132,9 @@ radv_trace_rays(struct radv_cmd_buffer *cmd_buffer, const VkTraceRaysIndirectCom
const struct radv_userdata_info *shader_loc =
radv_get_user_sgpr(rt_prolog, AC_UD_CS_TRAVERSAL_SHADER_ADDR);
if (shader_loc->sgpr_idx != -1) {
uint64_t raygen_va = cmd_buffer->state.shaders[MESA_SHADER_RAYGEN]->va;
uint64_t traversal_va = cmd_buffer->state.shaders[MESA_SHADER_INTERSECTION]->va;
radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
base_reg + shader_loc->sgpr_idx * 4, raygen_va, true);
base_reg + shader_loc->sgpr_idx * 4, traversal_va, true);
}
assert(cmd_buffer->cs->cdw <= cdw_max);

2
src/amd/vulkan/radv_pipeline.c
View file

@ -738,7 +738,7 @@ radv_get_shader_from_executable_index(struct radv_pipeline *pipeline, int index,
gl_shader_stage *stage)
{
if (pipeline->type == RADV_PIPELINE_RAY_TRACING) {
*stage = MESA_SHADER_RAYGEN;
*stage = MESA_SHADER_INTERSECTION;
return pipeline->shaders[*stage];
}

8
src/amd/vulkan/radv_pipeline_rt.c
View file

@ -442,7 +442,7 @@ radv_rt_pipeline_compile(struct radv_ray_tracing_pipeline *pipeline,
VkPipelineShaderStageCreateInfo stage = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
.pNext = NULL,
.stage = VK_SHADER_STAGE_RAYGEN_BIT_KHR,
.stage = VK_SHADER_STAGE_INTERSECTION_BIT_KHR,
.module = vk_shader_module_to_handle(&module),
.pName = "main",
};
@ -684,7 +684,7 @@ radv_rt_pipeline_create(VkDevice _device, VkPipelineCache _cache,
pipeline->base.base.shaders[MESA_SHADER_COMPUTE] = radv_create_rt_prolog(device);
combine_config(&pipeline->base.base.shaders[MESA_SHADER_COMPUTE]->config,
&pipeline->base.base.shaders[MESA_SHADER_RAYGEN]->config);
&pipeline->base.base.shaders[MESA_SHADER_INTERSECTION]->config);
postprocess_rt_config(&pipeline->base.base.shaders[MESA_SHADER_COMPUTE]->config,
device->physical_device->rad_info.gfx_level,
@ -716,8 +716,8 @@ radv_destroy_ray_tracing_pipeline(struct radv_device *device,
if (pipeline->base.base.shaders[MESA_SHADER_COMPUTE])
radv_shader_unref(device, pipeline->base.base.shaders[MESA_SHADER_COMPUTE]);
if (pipeline->base.base.shaders[MESA_SHADER_RAYGEN])
radv_shader_unref(device, pipeline->base.base.shaders[MESA_SHADER_RAYGEN]);
if (pipeline->base.base.shaders[MESA_SHADER_INTERSECTION])
radv_shader_unref(device, pipeline->base.base.shaders[MESA_SHADER_INTERSECTION]);
}
VKAPI_ATTR VkResult VKAPI_CALL