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radv: fix the CS regalloc hang workaround on GFX6 and few GFX7 chips

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RadeonSI uses a different terminology and info->blocks is actually the
number of threads, not the number of blocks (ie. info->grid).

Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15162>
This commit is contained in:
Samuel Pitoiset 2022-02-25 08:44:07 +01:00
parent 952679b944
commit d532da6e96
1 changed files with 3 additions and 1 deletions
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4
src/amd/vulkan/radv_cmd_buffer.c
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@ -7378,8 +7378,10 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf
{
bool has_prefetch = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline;
struct radv_shader *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
unsigned *cs_block_size = compute_shader->info.cs.block_size;
bool cs_regalloc_hang = cmd_buffer->device->physical_device->rad_info.has_cs_regalloc_hang_bug &&
info->blocks[0] * info->blocks[1] * info->blocks[2] > 256;
cs_block_size[0] * cs_block_size[1] * cs_block_size[2] > 256;
if (cs_regalloc_hang)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |