From dd48683cfd6daf07602b7e92b96baf3704489fd7 Mon Sep 17 00:00:00 2001 From: Caio Marcelo de Oliveira Filho Date: Thu, 29 Apr 2021 12:10:13 -0700 Subject: [PATCH] nir: Move shared_memory_explicit_layout bit into common shader_info Move it out of the "cs" sub-struct, since the bit can be used for other shader stages in the future. This also removes a subtle issue in spirv_to_nir: info.cs.shared_memory_explicit_layout was used without checking for the CS shader stage. It ended up being "harmless" since the effects also depended on presence of shared variables. Fixes: 5de6c5973a6 ("spirv: Implement SPV_KHR_workgroup_memory_explicit_layout") Reviewed-by: Jason Ekstrand Part-of: --- src/amd/vulkan/radv_shader.c | 2 +- src/compiler/nir/nir_lower_io.c | 2 +- src/compiler/shader_info.h | 12 ++++++------ src/compiler/spirv/spirv_to_nir.c | 4 ++-- src/intel/vulkan/anv_pipeline.c | 2 +- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 4a0d67408e1..2d9379a0b09 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -645,7 +645,7 @@ radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module * /* Lower deref operations for compute shared memory. */ if (nir->info.stage == MESA_SHADER_COMPUTE) { - if (!nir->info.cs.shared_memory_explicit_layout) { + if (!nir->info.shared_memory_explicit_layout) { NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, nir_var_mem_shared, shared_var_info); } NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_shared, nir_address_format_32bit_offset); diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c index 0624c7f74a8..6a6527019b5 100644 --- a/src/compiler/nir/nir_lower_io.c +++ b/src/compiler/nir/nir_lower_io.c @@ -2321,7 +2321,7 @@ nir_lower_vars_to_explicit_types(nir_shader *shader, progress |= lower_vars_to_explicit(shader, &shader->variables, nir_var_uniform, type_info); if (modes & nir_var_mem_shared) { - assert(!shader->info.cs.shared_memory_explicit_layout); + assert(!shader->info.shared_memory_explicit_layout); progress |= lower_vars_to_explicit(shader, &shader->variables, nir_var_mem_shared, type_info); } diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index d0c0dd28ddd..3dfb2cc0b2b 100644 --- a/src/compiler/shader_info.h +++ b/src/compiler/shader_info.h @@ -248,6 +248,12 @@ typedef struct shader_info { bool uses_control_barrier : 1; bool uses_memory_barrier : 1; + /** + * Shared memory types have explicit layout set. Used for + * SPV_KHR_workgroup_storage_explicit_layout. + */ + bool shared_memory_explicit_layout:1; + union { struct { /* Which inputs are doubles */ @@ -404,12 +410,6 @@ typedef struct shader_info { * Uses subgroup intrinsics which can communicate across a quad. */ bool uses_wide_subgroup_intrinsics; - - /** - * Shared memory types have explicit layout set. Used for - * SPV_KHR_workgroup_storage_explicit_layout. - */ - bool shared_memory_explicit_layout; } cs; /* Applies to both TCS and TES. */ diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 63c8e292aa7..68f21d4dd46 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -6101,11 +6101,11 @@ spirv_to_nir(const uint32_t *words, size_t word_count, nir_foreach_variable_with_modes(var, b->shader, nir_var_mem_shared) { if (glsl_type_is_interface(var->type)) { assert(b->options->caps.workgroup_memory_explicit_layout); - b->shader->info.cs.shared_memory_explicit_layout = true; + b->shader->info.shared_memory_explicit_layout = true; break; } } - if (b->shader->info.cs.shared_memory_explicit_layout) { + if (b->shader->info.shared_memory_explicit_layout) { unsigned size = 0; nir_foreach_variable_with_modes(var, b->shader, nir_var_mem_shared) { assert(glsl_type_is_interface(var->type)); diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index cabd6504b1b..9cc9326eb33 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -1784,7 +1784,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline, anv_pipeline_lower_nir(&pipeline->base, mem_ctx, &stage, layout); - if (!stage.nir->info.cs.shared_memory_explicit_layout) { + if (!stage.nir->info.shared_memory_explicit_layout) { NIR_PASS_V(stage.nir, nir_lower_vars_to_explicit_types, nir_var_mem_shared, shared_type_info); }