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radeonsi: fix reg_saved_mask for non graphics contexts

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The old code used to clear the bits, the new one set it. It should have
used `BITSET_CLEAR_RANGE` instead.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10286
Fixes: 17e01a9a9b ("radeonsi: merge context_reg_saved_mask and other_reg_saved_mask into a BITSET")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26657>
This commit is contained in:
Karol Herbst 2023-12-12 21:07:56 +01:00 • committed by Marge Bot
parent c3c3a8926a
commit de3190d36d
1 changed files with 2 additions and 2 deletions
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4
src/gallium/drivers/radeonsi/si_compute.c
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@ -1000,8 +1000,8 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
/* Skipping setting redundant registers on compute queues breaks compute. */
if (!sctx->has_graphics) {
BITSET_SET_RANGE(sctx->tracked_regs.reg_saved_mask,
SI_FIRST_TRACKED_OTHER_REG, SI_NUM_ALL_TRACKED_REGS - 1);
BITSET_CLEAR_RANGE(sctx->tracked_regs.reg_saved_mask,
SI_FIRST_TRACKED_OTHER_REG, SI_NUM_ALL_TRACKED_REGS - 1);
}
/* First emit registers. */