Marek Olšák 3120113ee7 radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9 ... MSAA 4x and 8x should only clear the first 2 samples because other samples are uncompressed. The compute shader only clears that subset of DCC. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>		2021-04-13 03:17:42 +00:00
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addrlib	amd/addrlib: expose DCC address equations to drivers	2021-04-13 03:17:42 +00:00
ci	radv: change RADV_FORCE_FAMILY to use family name instead of LLVM processor name	2021-04-05 06:53:55 +00:00
common	radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9	2021-04-13 03:17:42 +00:00
compiler	aco: fix 16-bit f2{u8,i8} on GFX6/7	2021-04-12 16:19:46 +00:00
llvm	nir: Extract shader_info->cs.shared_size out of union.	2021-04-08 14:39:28 +00:00
registers	amd: fix parsing the last dword of DMA_DATA packets	2021-04-02 12:05:00 +00:00
vulkan	ac,radeonsi: rewrite DCC retiling without the DCC retile map	2021-04-13 03:17:42 +00:00
.clang-format	radv: Add clang-format for AMD code.	2021-04-10 03:31:32 +02:00
Android.addrlib.mk	android: amd/addrlib: define endianess to build	2021-03-27 01:54:49 +01:00
Android.common.mk
Android.compiler.mk
Android.mk
Makefile.sources	ac: add ac_get_family_name() helper	2021-04-05 06:53:55 +00:00
meson.build