Lucas Stach 52f6c8cc31 etnaviv: align TS surface size to number of pixel pipes ... The TS surface gets cleared by a tiled RS fill. If the chip has more than 1 pixel pipe the size of the TS surface needs to be aligned so that each pipe address matches a tile start, otherwise the RS will hang. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>		2017-04-11 16:52:22 +02:00
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amd	radv: Implement pipeline statistics queries.	2017-04-11 09:33:17 +02:00
compiler	glsl: use the BA1 macro for textureQueryLevels()	2017-04-11 10:24:57 +02:00
egl	Android: drop Android 4.4 (KitKat) support	2017-03-22 17:53:31 +00:00
gallium	etnaviv: align TS surface size to number of pixel pipes	2017-04-11 16:52:22 +02:00
gbm	gbm: Assert modifiers and count are copacetic	2017-04-09 09:29:57 -07:00
getopt
glx	glx: silence uninitialized var warning	2017-04-07 13:46:44 -06:00
gtest
hgl
intel	intel/blorp: Use ISL for emitting depth/stencil/hiz	2017-04-10 07:57:21 -07:00
loader	loader: use drmGetDevice[s]2 API	2017-03-15 11:37:55 +00:00
mapi	mesa: add GL_ARB_shader_ballot boilerplate	2017-04-05 15:25:40 +02:00
mesa	i965: Fix wonky indentation left by brw_bo_alloc_tiled rename.	2017-04-10 23:25:13 -07:00
util	util: fix MSVC warning in u_align_u32()	2017-04-03 13:09:05 -06:00
vulkan	vulkan/wsi/wayland: Pass damage through to the compositor	2017-04-03 13:51:08 -07:00
Makefile.am	intel/vulkan: Get rid of recursive make	2017-03-13 11:16:35 +00:00
SConscript