Nanley Chery 82822bc549 iris: Allow for non-Y-tiled aux allocation ... The Gen12 CCS is not Y-tiled. Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>		2019-10-28 10:47:05 -07:00
..
amd	util: rename list_empty() to list_is_empty()	2019-10-28 11:24:38 +00:00
broadcom	util: rename list_empty() to list_is_empty()	2019-10-28 11:24:38 +00:00
compiler	glsl: Initialize all fields of ir_variable in constructor	2019-10-28 12:49:15 +00:00
drm-shim
egl	egl: implement new functions from EGL_EXT_image_flush_external	2019-10-25 19:59:04 -04:00
etnaviv	util: remove LIST_IS_EMPTY macro	2019-10-28 11:24:39 +00:00
freedreno	util: remove LIST_IS_EMPTY macro	2019-10-28 11:24:39 +00:00
gallium	iris: Allow for non-Y-tiled aux allocation	2019-10-28 10:47:05 -07:00
gbm	gbm: Add GBM_MAX_PLANES definition	2019-10-18 13:18:28 +00:00
getopt
glx
gtest
hgl
imgui
intel	isl/drm: Map HiZ and CCS tilings to Y	2019-10-28 10:47:05 -07:00
loader
mapi	Revert "mapi: Inline call x86_current_tls."	2019-10-25 11:31:51 -05:00
mesa	i965/miptree: Avoid -Wswitch for the Gen12 aux modes	2019-10-28 10:47:05 -07:00
panfrost	pan/midgard: Express allocated registers as offsets	2019-10-25 08:45:39 -04:00
util	util: remove LIST_IS_EMPTY macro	2019-10-28 11:24:39 +00:00
vulkan	util: rename list_empty() to list_is_empty()	2019-10-28 11:24:38 +00:00
meson.build
SConscript