Robert Foss 19af208c7d virgl: add assert and missing function parameter ... Verify the pipe_fd_type to be of PIPE_FD_TYPE_NATIVE_SYNC. Fixes: d1a1c21e76 "virgl: native fence fd support" Suggested-by: Eric Engestrom <eric.engestrom@intel.com> Signed-off-by: Robert Foss <robert.foss@collabora.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>		2018-11-21 15:59:00 +01:00
..
etnaviv	etnaviv: use dummy RT buffer when rendering without color buffer	2018-11-19 15:48:10 +01:00
freedreno	nir: Make nir_lower_clip_vs optionally work with variables.	2018-11-19 14:33:16 -08:00
i915	util: Move os_misc to util	2018-10-30 14:32:52 -07:00
imx
llvmpipe	meson: Add tests to suites	2018-11-20 09:09:22 -08:00
nouveau	nv50/ir/ra: enforce max register requirement, and change spill order	2018-11-16 22:43:52 -05:00
pl111
r300	meson: Add tests to suites	2018-11-20 09:09:22 -08:00
r600	r600: clean up the GS ring buffers when the context is destroyed	2018-11-21 10:34:17 +01:00
radeon	radeonsi: stop command submission with PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET only	2018-11-09 14:55:04 -05:00
radeonsi	radeonsi: go back to using bottom-of-pipe for beginning of TIME_ELAPSED	2018-11-20 21:18:48 -05:00
softpipe	util: Move os_misc to util	2018-10-30 14:32:52 -07:00
svga	Gallium: Add format PIPE_FORMAT_R8_SRGB	2018-11-02 11:52:44 +01:00
swr	configure: allow building with python3	2018-10-31 19:15:50 +00:00
tegra	gallium: rework PIPE_HANDLE_USAGE_* flags	2018-10-30 16:03:02 -04:00
v3d	v3d: Fix double-swapping of R/B on V3D 4.1	2018-11-15 11:12:54 -08:00
vc4	nir: Make nir_lower_clip_vs optionally work with variables.	2018-11-19 14:33:16 -08:00
virgl	virgl: add assert and missing function parameter	2018-11-21 15:59:00 +01:00