Paulo Zanoni c2db19f496 anv: setup the TR-TT vma heap ... "16TB ought to be enough for anybody." - Probably some Intel graphics hardware engineer TR-TT addresses are fixed regardless of the platform's gtt_size. Unconditionally reserve this space for it: our total 48bit address space is 256tb and TR-TT takes 16tb out of it (1/16th). Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26036>		2023-11-04 02:06:53 +00:00
..
blorp	blorp: handle binding table & surface state allocation failures	2023-10-30 14:47:18 +00:00
ci	anv: uninitialize queues before utrace	2023-10-19 09:45:36 +00:00
common	intel/xehp+: Import algorithm for TBIMR tiling parameter calculation.	2023-10-27 14:48:29 -07:00
compiler	intel/compiler: migrate WA 14013672992 to use WA framework	2023-11-02 16:39:25 +00:00
dev	intel/dev: fix intel_device_info_is_adln check	2023-10-30 11:20:41 +00:00
ds	intel/ds: provide names for different events of a timeline's row	2023-10-17 11:19:13 +00:00
genxml	intel/genxml: add the Gen12+ TR-TT registers	2023-11-04 02:06:52 +00:00
isl	docs/isl: use hawkmoth instead of doxygen	2023-10-26 16:13:26 +00:00
nullhw-layer	meson: support installation tags	2023-09-11 13:00:45 +00:00
perf	intel: Move i915_drm.h specific code from common/intel_gem.h to common/i915/intel_gem.h	2023-07-28 15:36:52 +00:00
tools	intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c	2023-09-06 01:39:53 +00:00
vulkan	anv: setup the TR-TT vma heap	2023-11-04 02:06:53 +00:00
vulkan_hasvk	vulkan: Consolidate common ICD methods	2023-11-03 20:01:14 +00:00
meson.build	intel: Only build perf if drivers or tools are enabled	2023-08-31 21:53:19 +00:00