Eric Anholt ec3bc5da74 v3d: Use the ra_alloc_contig_reg_class() function to speed up RA. ... It means we don't need to do the n^2 loop over the regs to set up the pq values, nor do we need the register conflicts lists. Acked-by: Erico Nunes <nunes.erico@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>		2021-06-04 19:08:57 +00:00
..
ci	v3dv: don't keep an open file descriptor for imported fences/semaphores	2021-06-02 09:58:47 +00:00
cle	intel: Rename gen_10 to ver_10	2021-04-20 20:06:34 +00:00
clif
common	broadcom/common: move v3d_tiling to common	2021-06-04 13:00:40 +02:00
compiler	v3d: Use the ra_alloc_contig_reg_class() function to speed up RA.	2021-06-04 19:08:57 +00:00
drm-shim	vc4: add drm-shim	2021-01-28 16:14:06 +00:00
qpu	broadcom/qpu: rename from VC5 to V3D	2021-04-29 11:22:12 +02:00
simulator	v3d/simulator: use BFC/RFC registers to wait for bin/render to complete	2021-06-01 12:22:28 +02:00
vulkan	broadcom/common: move v3d_tiling to common	2021-06-04 13:00:40 +02:00
.editorconfig
Android.cle.mk
Android.genxml.mk
Android.mk
Makefile.sources
meson.build	broadcom/common: move v3d_tiling to common	2021-06-04 13:00:40 +02:00