c1afe86299
The round up in 'next_address_8kb = DIV_ROUND_UP(push_constant_kb, 8)' was not decreasing the amount of URB available for Mesh and Task, what could cause an over allocation of URB. There was also no minimum entries enforcement for Mesh and Task, what could cause 0 r.mesh_entries to be set in a case where tue_size_dw is 90% > than mue_size_dw. Same for r.task_entries when Task is enabled. Also adding a few more asserts to help debug. This fixes at least dEQP-VK.mesh_shader.ext.properties.mesh_payload_size in LNL but it has potential to fixes other Mesh tests as well. Cc: mesa-stable Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27555> (cherry picked from commit d0fba810b3d334191ead4f16f5ba786250a70c32) |
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| .. | ||
| i915 | ||
| tests | ||
| xe | ||
| intel_aux_map.c | ||
| intel_aux_map.h | ||
| intel_batch_decoder.c | ||
| intel_batch_decoder_stub.c | ||
| intel_buffer_alloc.h | ||
| intel_clflushopt.c | ||
| intel_decoder.c | ||
| intel_decoder.h | ||
| intel_defines.h | ||
| intel_disasm.c | ||
| intel_disasm.h | ||
| intel_engine.c | ||
| intel_engine.h | ||
| intel_gem.c | ||
| intel_gem.h | ||
| intel_genX_state.h | ||
| intel_guardband.h | ||
| intel_hang_dump.h | ||
| intel_l3_config.c | ||
| intel_l3_config.h | ||
| intel_measure.c | ||
| intel_measure.h | ||
| intel_mem.c | ||
| intel_mem.h | ||
| intel_pixel_hash.h | ||
| intel_sample_positions.c | ||
| intel_sample_positions.h | ||
| intel_tiled_render.h | ||
| intel_urb_config.c | ||
| intel_uuid.c | ||
| intel_uuid.h | ||
| meson.build | ||
| mi_builder.h | ||