mesa/src
Iago Toral Quiroga f1873956db i965/vec4: fix splitting of interleaved attributes
When we split an instruction that reads an uniform value
(vstride 0) we need to respect the vstride on the second
half of the instruction (that is, the second half should
read the same region as the first).

We were doing this already, but we didn't account for
stages that have interleaved input attributes which also
have a vstride of 0 and need the same treatment.

Fixes the following on Haswell:
KHR-GL45.enhanced_layouts.varying_locations
KHR-GL45.enhanced_layouts.varying_array_locations
KHR-GL45.enhanced_layouts.varying_structure_locations

Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Andres Gomez <agomez@igalia.com>
2017-11-24 09:24:06 +01:00
..
amd amd: build addrlib with C++11 2017-11-20 16:26:28 +01:00
broadcom broadcom/vc5: Fix BASE_LEVEL handling with txl. 2017-11-22 10:56:31 -08:00
compiler nir/gather_info: recognize load_patch_vertices_in as a system value 2017-11-22 08:03:55 +01:00
egl egl: Convert int to attrib in eglGetPlatformDisplay 2017-11-17 16:43:16 -05:00
gallium etnaviv: Emit vertex buffers consecutively 2017-11-23 22:24:51 +01:00
gbm wayland-drm: static inline wayland_drm_buffer_get 2017-11-08 14:40:12 +00:00
getopt
glx meson: replace with_*dri with with_dri_platform 2017-11-22 12:47:43 -08:00
gtest
hgl
intel i965/vec4: fix splitting of interleaved attributes 2017-11-24 09:24:06 +01:00
loader loader/dri3: Improve dri3 thread-safety 2017-11-13 12:43:39 +01:00
mapi meson: add variable for mapi_abi.py instead of going back up the tree 2017-11-23 09:44:16 +00:00
mesa meson: Enable SSE4.1 optimizations 2017-11-22 12:46:00 -08:00
util util/u_queue: really use futex-based fences 2017-11-20 18:15:53 +01:00
vulkan
git_sha1.h.in
Makefile.am wayland-drm: static inline wayland_drm_buffer_get 2017-11-08 14:40:12 +00:00
meson.build meson: reorder subdirs to avoid directly including more than one level 2017-11-23 09:44:16 +00:00
SConscript