mesa/docs/gallium
Vasily Khoruzhick 3bb192a15b gallium: add PIPE_CAP_PREFER_POT_ALIGNED_VARYINGS
Driver should enable this cap if it prefers varyings to be aligned
to power of two in a slot, i.e. vec4 in .xyzw, vec3 in .xyz, vec2 in .xy
or .zw

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13151>
2021-11-15 22:52:55 +00:00
..
cso gallium: add rasterizer depth_clamp enable bit 2021-09-09 18:29:26 +00:00
buffermapping.rst
context.rst
cso.rst
debugging.rst
distro.rst
format.rst
glossary.rst
index.rst
intro.rst
pipeline.txt
postprocess.rst
resources.rst
screen.rst gallium: add PIPE_CAP_PREFER_POT_ALIGNED_VARYINGS 2021-11-15 22:52:55 +00:00
tgsi.rst