Samuel Pitoiset 96403c1ec4 radv: allow fast clears for concurrent images if comp-to-single is supported ... Only GFX10+ is affected because older chips don't support comp-to-single. For them, we need to implement FCE on compute with DCC and eventually CMASK. Fixes the gap between concurrent vs exclusive queue with Scarlet Nexus, also gives a boost with Doom Eternal. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12088>		2021-08-10 12:52:14 +02:00
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addrlib	amd/addrlib: expose CMASK address equations to drivers on GFX10+	2021-08-05 06:37:09 +00:00
ci	ci: update to VK-GL-CTS 1.2.7.0	2021-07-30 20:02:13 +00:00
common	ac/surface: implement CmaskAddrFromCoord in NIR on GFX10+	2021-08-05 06:37:09 +00:00
compiler	aco: calculate correct register demand for branch instructions	2021-08-05 12:01:58 +00:00
llvm	ac/llvm: implement v2f16 fsat	2021-08-02 10:02:51 +00:00
registers	amd/registers: fix fields conflict detection	2021-07-30 08:50:38 +00:00
vulkan	radv: allow fast clears for concurrent images if comp-to-single is supported	2021-08-10 12:52:14 +02:00
.clang-format	radv: Add clang-format for AMD code.	2021-04-10 03:31:32 +02:00
meson.build