d3d12: GL4.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26180>
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4 changed files with 29 additions and 5 deletions
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@ -210,11 +210,11 @@ GL 4.4, GLSL 4.40 -- all DONE: freedreno/a6xx, nvc0, r600, radeonsi, llvmpipe, v
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GL_ARB_texture_stencil8 DONE (freedreno, nv50, softpipe, v3d, panfrost, asahi)
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GL_ARB_vertex_type_10f_11f_11f_rev DONE (freedreno, nv50, softpipe, panfrost, asahi, crocus)
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GL 4.5, GLSL 4.50 -- all DONE: freedreno/a6xx, nvc0, r600, radeonsi, llvmpipe, virgl, zink, iris, crocus/gen7.5+
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GL 4.5, GLSL 4.50 -- all DONE: freedreno/a6xx, nvc0, r600, radeonsi, llvmpipe, virgl, zink, iris, crocus/gen7.5+, d3d12
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GL_ARB_ES3_1_compatibility DONE (freedreno/a6xx, softpipe)
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GL_ARB_clip_control DONE (freedreno, nv50, softpipe, lima, d3d12, crocus, asahi)
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GL_ARB_conditional_render_inverted DONE (freedreno, nv50, softpipe, panfrost, d3d12, asahi, crocus/gen6+)
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GL_ARB_clip_control DONE (freedreno, nv50, softpipe, lima, crocus, asahi)
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GL_ARB_conditional_render_inverted DONE (freedreno, nv50, softpipe, panfrost, asahi, crocus/gen6+)
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GL_ARB_cull_distance DONE (freedreno/a6xx, nv50, softpipe, crocus/gen6+)
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GL_ARB_derivative_control DONE (freedreno/a3xx+, nv50, softpipe, asahi, crocus/gen7+)
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GL_ARB_direct_state_access DONE (all drivers)
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@ -49,3 +49,7 @@ spec@arb_enhanced_layouts@execution@component-layout@vs-fs-array-dvec3,Crash
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# TODO: Need to investigate and debug
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spec@arb_enhanced_layouts@execution@component-layout@vs-gs-fs-double,Fail
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spec@arb_tessellation_shader@execution@dvec3-vs-tcs-tes,Fail
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# WARP bug: Due to SIMT, the FS loop runs 4 times, and all 4 threads end up with
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# the final value from the SSBO instead of remembering their own value they computed.
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spec@glsl-4.50@execution@ssbo-atomiccompswap-int,Fail
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@ -2377,6 +2377,21 @@ d3d12_memory_barrier(struct pipe_context *pctx, unsigned flags)
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}
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}
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static void
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d3d12_texture_barrier(struct pipe_context *pctx, unsigned flags)
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{
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struct d3d12_context *ctx = d3d12_context(pctx);
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/* D3D doesn't really have an equivalent in the legacy barrier model. When using enhanced barriers,
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* this could be a more specific global barrier. But for now, just flush the world with an aliasing barrier. */
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D3D12_RESOURCE_BARRIER aliasingBarrier;
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aliasingBarrier.Type = D3D12_RESOURCE_BARRIER_TYPE_ALIASING;
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aliasingBarrier.Flags = D3D12_RESOURCE_BARRIER_FLAG_NONE;
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aliasingBarrier.Aliasing.pResourceBefore = nullptr;
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aliasingBarrier.Aliasing.pResourceAfter = nullptr;
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ctx->cmdlist->ResourceBarrier(1, &aliasingBarrier);
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}
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static void
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d3d12_set_patch_vertices(struct pipe_context *pctx, uint8_t patch_vertices)
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{
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@ -2534,6 +2549,7 @@ d3d12_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
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ctx->base.fence_server_sync = d3d12_wait;
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ctx->base.memory_barrier = d3d12_memory_barrier;
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ctx->base.texture_barrier = d3d12_texture_barrier;
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ctx->base.get_sample_position = u_default_get_sample_position;
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@ -193,9 +193,9 @@ d3d12_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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return 1;
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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return 440;
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return 450;
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case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
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return 440;
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return 450;
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case PIPE_CAP_ESSL_FEATURE_LEVEL:
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return 310;
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@ -336,6 +336,10 @@ d3d12_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
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case PIPE_CAP_QUERY_TIME_ELAPSED:
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case PIPE_CAP_FS_FINE_DERIVATIVE:
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case PIPE_CAP_CULL_DISTANCE:
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case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
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case PIPE_CAP_TEXTURE_BARRIER:
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return 1;
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case PIPE_CAP_QUERY_BUFFER_OBJECT:
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