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asahi: fix eMRT + background load interaction

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for when some render targets are spilled only. prevents regression in
KHR-GLES31.core.draw_buffers_indexed.color_masks

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26963>
This commit is contained in:
Alyssa Rosenzweig 2024-01-09 20:41:47 -04:00
parent 0610891c7c
commit 2728995f12
2 changed files with 14 additions and 5 deletions
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2
src/asahi/lib/agx_meta.c
View file

@ -92,7 +92,7 @@ build_background_op(nir_builder *b, enum agx_meta_op op, unsigned rt,
} }
tex->coord_components = layered ? 3 : 2; tex->coord_components = layered ? 3 : 2;
tex->texture_index = rt; tex->texture_index = rt * 2;
nir_def_init(&tex->instr, &tex->def, 4, 32); nir_def_init(&tex->instr, &tex->def, 4, 32);
nir_builder_instr_insert(b, &tex->instr); nir_builder_instr_insert(b, &tex->instr);

17
src/gallium/drivers/asahi/agx_state.c
View file

@ -2779,6 +2779,10 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render)
/* Construct the key */ /* Construct the key */
struct agx_meta_key key = {.tib = batch->tilebuffer_layout}; struct agx_meta_key key = {.tib = batch->tilebuffer_layout};
bool needs_textures_for_spilled_rts =
agx_tilebuffer_spills(&batch->tilebuffer_layout) && !partial_render &&
!store;
for (unsigned rt = 0; rt < PIPE_MAX_COLOR_BUFS; ++rt) { for (unsigned rt = 0; rt < PIPE_MAX_COLOR_BUFS; ++rt) {
struct pipe_surface *surf = batch->key.cbufs[rt]; struct pipe_surface *surf = batch->key.cbufs[rt];
@ -2824,6 +2828,12 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render)
for (unsigned rt = 0; rt < PIPE_MAX_COLOR_BUFS; ++rt) { for (unsigned rt = 0; rt < PIPE_MAX_COLOR_BUFS; ++rt) {
if (key.op[rt] == AGX_META_OP_LOAD) { if (key.op[rt] == AGX_META_OP_LOAD) {
/* Each reloaded render target is textured */ /* Each reloaded render target is textured */
needs_sampler = true;
/* Will be uploaded later, this would be clobbered */
if (needs_textures_for_spilled_rts)
continue;
struct agx_ptr texture = struct agx_ptr texture =
agx_pool_alloc_aligned(&batch->pool, AGX_TEXTURE_LENGTH, 64); agx_pool_alloc_aligned(&batch->pool, AGX_TEXTURE_LENGTH, 64);
struct pipe_surface *surf = batch->key.cbufs[rt]; struct pipe_surface *surf = batch->key.cbufs[rt];
@ -2835,12 +2845,12 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render)
agx_pack_texture(texture.cpu, rsrc, surf->format, &sampler_view); agx_pack_texture(texture.cpu, rsrc, surf->format, &sampler_view);
agx_usc_pack(&b, TEXTURE, cfg) { agx_usc_pack(&b, TEXTURE, cfg) {
cfg.start = rt; /* Shifted to match eMRT indexing, could be optimized */
cfg.start = rt * 2;
cfg.count = 1; cfg.count = 1;
cfg.buffer = texture.gpu; cfg.buffer = texture.gpu;
} }
needs_sampler = true;
} else if (key.op[rt] == AGX_META_OP_CLEAR) { } else if (key.op[rt] == AGX_META_OP_CLEAR) {
assert(batch->uploaded_clear_color[rt] && "set when cleared"); assert(batch->uploaded_clear_color[rt] && "set when cleared");
agx_usc_uniform(&b, 4 + (8 * rt), 8, batch->uploaded_clear_color[rt]); agx_usc_uniform(&b, 4 + (8 * rt), 8, batch->uploaded_clear_color[rt]);
@ -2864,8 +2874,7 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render)
} }
} }
if (agx_tilebuffer_spills(&batch->tilebuffer_layout) && !partial_render && if (needs_textures_for_spilled_rts) {
!store) {
/* Upload texture/PBE descriptors for each render target so we can clear /* Upload texture/PBE descriptors for each render target so we can clear
* spilled render targets. * spilled render targets.
*/ */